From: lkcl <lkcl@web>
Date: Fri, 27 May 2022 19:38:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2056
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6783ee9805610996d24676f5a8f6ee59af71522d;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 506a9034d..0ac865971 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -115,8 +115,9 @@ mantissa may be achieved.
 
 *IBM may consider it worthwhile to extend these two instructions to
 v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that
-`pfmvis` load a full FP32 immediate and `pfrlsi` extend the lower
-32-bits to construct a full FP64 immediate.*
+`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the four high
+missing exponent bits (8 to 10) and the lower additional
+28 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*
 
 ## Load BF16 Immediate