From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Feb 2015 13:44:36 +0000 (+0100)
Subject: mac: fix missing core csr generation
X-Git-Tag: 24jan2021_ls180~2604^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67958f74484e18caa69ddd862158e1fad1f77f34;p=litex.git

mac: fix missing core csr generation
---

diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 5e88646b..1517b7bd 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR):
 			self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
 			self.comb += Port.connect(self.interface, self.core)
 			self.ev, self.bus = self.interface.sram.ev, self.interface.bus
-			self.csrs = self.interface.get_csrs()
+			self.csrs = self.interface.get_csrs() + self.core.get_csrs()
 		elif interface == "dma":
 			raise NotImplementedError
 		else: