From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 14 Nov 2016 00:10:30 +0000 (-0800)
Subject: Fix 32-bit host portability bug
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=679d5f5e927a0a59bbaaab33955ded79e860cded;p=riscv-isa-sim.git

Fix 32-bit host portability bug
---

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 105908e..34bcf99 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -202,7 +202,7 @@ private:
   static const reg_t TLB_ENTRIES = 256;
   // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a
   // trigger match before completing an access.
-  static const reg_t TLB_CHECK_TRIGGERS = 1L<<63;
+  static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63;
   char* tlb_data[TLB_ENTRIES];
   reg_t tlb_insn_tag[TLB_ENTRIES];
   reg_t tlb_load_tag[TLB_ENTRIES];