From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 May 2019 20:13:10 +0000 (-0700)
Subject: Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
X-Git-Tag: yosys-0.9~113
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67a4850e3505e97bcb01fb02a688beee89af6e76;p=yosys.git

Merge pull request #1036 from YosysHQ/eddie/xilinx_dram

Add "min bits" and "min wports" to xilinx dram rules
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67a4850e3505e97bcb01fb02a688beee89af6e76