From: Xan Date: Wed, 25 Apr 2018 04:53:54 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5564 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67b771cf089321852e5fcf6f28c931f1b7d87d50;p=libreriscv.git --- diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn index 75d7b3c8c..a9593b2d6 100644 --- a/Harmonised_RVV/Packed_SIMD.mdwn +++ b/Harmonised_RVV/Packed_SIMD.mdwn @@ -10,7 +10,7 @@ RVP implementations may choose to load/store to/from Integer register file (rath * Thus, RVP implementations have a choice of providing a dedicated Vector register file, or sharing the integer register file, but not both simultaneously. (Supporting both would need a CSR mode switch bit). * If integer register file is used for vector operations, any callee saved registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions, before being used as vector registers (this register saving behaviour is harmless but redundant when RVP code is run on a machine with a dedicated vector reg file). -##### VLDX, VSTX, VLDS, VSTS are not supported in RVP +##### VLDX, VSTX, VLDS, VSTS are not supported in hardware To keep RVP implementations simple, these instructions will trap, and may be implemented as software emulation ##### Default register "banks" and types