From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 Jul 2023 03:09:58 +0000 (+0100)
Subject: series of cosmetic changes for PDF layout, also recommending moving
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67bbeb1fd7e4d2413c00d889c925303657a4407f;p=libreriscv.git

series of cosmetic changes for PDF layout, also recommending moving
the pseudocode for the cffpr instruction to an Appendix as it is too large
to go into the instruction itself (like many FP operations that also have
helper-functions in the appendix)
---

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index 378022d43..ae74582d0 100644
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -31,6 +31,8 @@ Tables that are used by
 
 ----------
 
+\newpage{}
+
 # Move To/From Floating-Point Register Instructions
 
 These instructions perform a copy from one register file to another, as if by
@@ -335,6 +337,12 @@ Special Registers altered:
 |-----|------|-------|-------|-------|----|-------|----|---------|
 | PO  | RT   | IT    | CVM   | FRB   | OE | XO    | Rc | XO-Form |
 
+**TODO: move to Appendix (it's too large. also it really should be executable
+and pulled in "automatically" from the openpower-isa directory, into the
+PDF but also as an ikiwiki underlay - just not here: in the RFC directory)**
+
+For the pseudocode of this instruction see Appendix {insert automated reference}
+
 ```
     # based on xscvdpuxws
     reset_xflags()
@@ -448,7 +456,7 @@ Convert from 64-bit float in FRB to a unsigned/signed 32/64-bit integer
 in RT, with the conversion overflow/rounding semantics following the
 chosen `CVM` value. `FPSCR` is modified and exceptions are raised as usual.
 
-These instructions have an Rc=1 mode which sets CR0 in the normal
+This instruction has an Rc=1 mode which sets CR0 in the normal
 way for any instructions producing a GPR result.  Additionally, when OE=1,
 if the numerical value of the FP number is not 100% accurately preserved
 (due to truncation or saturation and including when the FP number was
@@ -485,3 +493,4 @@ Special Registers altered:
 | `cffprud. RT, FRB, CVM`  | `cffpr. RT, FRB, CVM, 3`  |
 | `cffprudo RT, FRB, CVM`  | `cffpro RT, FRB, CVM, 3`  |
 | `cffprudo. RT, FRB, CVM` | `cffpro. RT, FRB, CVM, 3` |
+
diff --git a/openpower/sv/rfc/ls006.fpintmv.mdwn b/openpower/sv/rfc/ls006.fpintmv.mdwn
index 806c7b129..ab231c4e3 100644
--- a/openpower/sv/rfc/ls006.fpintmv.mdwn
+++ b/openpower/sv/rfc/ls006.fpintmv.mdwn
@@ -69,9 +69,11 @@ efficient data transfer (both bitwise copy and Integer <-> FP conversion)
 instructions that transfer directly between FPRs and GPRs without needing
 to go through memory.
 
-IEEE 754 doesn't specify what results are obtained when converting a NaN
-or out-of-range floating-point value to integer, so different programming
-languages and ISAs have made different choices.  Below is an overview
+IEEE 754 does not specify what results are obtained when converting a NaN
+or out-of-range floating-point value to integer: consequently, different
+programming
+languages and ISAs have made different choices, making binary portability
+very difficult.  Below is an overview
 of the different variants, listing the languages and hardware that
 implements each variant.
 
@@ -109,8 +111,6 @@ Add the following entries to:
 
 \newpage{}
 
-----------
-
 # Instruction Formats
 
 Add the following entries to Book I 1.6.1.19 XO-FORM:
@@ -154,8 +154,6 @@ Add new fields:
 
 \newpage{}
 
-----------
-
 # Appendices
 
     Appendix E Power ISA sorted by opcode