From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 21:12:47 +0000 (+0100)
Subject: allow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface
X-Git-Tag: div_pipeline~271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67cccdc458b71154a3ae9c4a3af2a3c183f4599e;p=soc.git

allow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface
---

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 97a42c86..b1c888d1 100644
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -31,10 +31,14 @@ from nmigen import Elaboratable, Module, Signal
 
 class Pi2LSUI(Elaboratable):
 
-    def __init__(self, name, regwid=64, addrwid=48):
+    def __init__(self, name, pi=None, lsui=None, regwid=64, addrwid=48):
         self.addrbits = 4
-        self.pi = PortInterface(name="%s_pi", regwid, addrwid)
-        self.lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
+        if pi is None:
+            pi = PortInterface(name="%s_pi", regwid, addrwid)
+        self.pi = pi
+        if lsui = None:
+            lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
+        self.lsui = lsui
 
     def splitaddr(self, addr):
         """split the address into top and bottom bits of the memory granularity