From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 Aug 2020 14:05:05 +0000 (+0100)
Subject: move regspec / rdflag decoding functions out of PowerDecode2
X-Git-Tag: semi_working_ecp5~354
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67ce9da3f5069511b19b071c15b346ee0cebdeb5;p=soc.git

move regspec / rdflag decoding functions out of PowerDecode2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index e693ed3d..97f2b530 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -758,28 +758,15 @@ class PowerDecode2(Elaboratable):
         comb += do.msr.eq(self.state.msr)  # copy of MSR "state"
         comb += do.cia.eq(self.state.pc)  # copy of PC "state"
 
-    def regspecmap_read(self, regfile, regname):
-        """regspecmap_read: provides PowerDecode2 with an encoding relationship
-        to Function Unit port regfiles (read-enable, read regnum, write regnum)
-        regfile and regname arguments are fields 1 and 2 from a given regspec.
-        """
-        return regspec_decode_read(self.e, regfile, regname)
 
-    def regspecmap_write(self, regfile, regname):
-        """regspecmap_write: provides PowerDecode2 with an encoding relationship
-        to Function Unit port regfiles (write port, write regnum)
-        regfile and regname arguments are fields 1 and 2 from a given regspec.
-        """
-        return regspec_decode_write(self.e, regfile, regname)
-
-    def rdflags(self, cu):
-        rdl = []
-        for idx in range(cu.n_src):
-            regfile, regname, _ = cu.get_in_spec(idx)
-            rdflag, read = self.regspecmap_read(regfile, regname)
-            rdl.append(rdflag)
-        print("rdflags", rdl)
-        return Cat(*rdl)
+def get_rdflags(e, cu):
+    rdl = []
+    for idx in range(cu.n_src):
+        regfile, regname, _ = cu.get_in_spec(idx)
+        rdflag, read = regspec_decode_read(e, regfile, regname)
+        rdl.append(rdflag)
+    print("rdflags", rdl)
+    return Cat(*rdl)
 
 
 if __name__ == '__main__':
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index e5b03ffc..477eb78a 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -22,13 +22,16 @@ before allowing a new instruction to proceed.
 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
 from nmigen.cli import rtlil
 
+from soc.decoder.power_regspec_map import regspec_decode_read
+from soc.decoder.power_regspec_map import regspec_decode_write
+
 from nmutil.picker import PriorityPicker
 from nmutil.util import treereduce
 
 from soc.fu.compunits.compunits import AllFunctionUnits
 from soc.regfile.regfiles import RegFiles
 from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.power_decoder2 import PowerDecode2, get_rdflags
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
 from soc.config.test.test_loadstore import TestMemPspec
@@ -125,6 +128,7 @@ class NonProductionCore(Elaboratable):
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
         dec2 = self.pdecode2
+        e = dec2.e # to execute
 
         # enable-signals for each FU, get one bit for each FU (by name)
         fu_enable = Signal(len(fus), reset_less=True)
@@ -168,7 +172,7 @@ class NonProductionCore(Elaboratable):
                             comb += fu.oper_i.eq_from_execute1(dec2.e)
                             comb += fu.issue_i.eq(self.issue_i)
                             comb += self.busy_o.eq(fu.busy_o)
-                            rdmask = dec2.rdflags(fu)
+                            rdmask = get_rdflags(e, fu)
                             comb += fu.rdmaskn.eq(~rdmask)
 
         return fu_bitdict
@@ -426,6 +430,7 @@ class NonProductionCore(Elaboratable):
         dec2 = self.pdecode2
         regs = self.regs
         fus = self.fus.fus
+        e = dec2.e # decoded instruction to execute
 
         # dictionary of lists of regfile ports
         byregfiles = {}
@@ -439,11 +444,11 @@ class NonProductionCore(Elaboratable):
                     (regfile, regname, wid) = fu.get_out_spec(idx)
                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
                 if readmode:
-                    rdflag, read = dec2.regspecmap_read(regfile, regname)
+                    rdflag, read = regspec_decode_read(e, regfile, regname)
                     write = None
                 else:
                     rdflag, read = None, None
-                    wrport, write = dec2.regspecmap_write(regfile, regname)
+                    wrport, write = regspec_decode_write(e, regfile, regname)
                 if regfile not in byregfiles:
                     byregfiles[regfile] = {}
                     byregfiles_spec[regfile] = {}