From: lkcl <lkcl@web>
Date: Sun, 9 Oct 2022 21:36:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67def841c139e789fee116cbc72d0e8cd074ae09;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 59e876ab3..ba359a93c 100644
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -56,15 +56,15 @@
 **Keywords**:
 
 ```
-    FPR, Floating-point, Load-immediate, BF16, FP32
+    FPR, Floating-point, Load-immediate, BF16, bfloat16, FP32
 ```
 
 **Motivation**
 
-Similar to `lxvkq` but extended to a full BF16 with one
+Similar to `lxvkq` but extended to a full bfloat16 with one
 32-bit instruction and a full FP32 in two 32-bit instructions
 these instructions always save a Data Load and associated L1
-and TLB lookup. Even clearing an FPR to zero presently requires Load.
+and TLB lookup. Even quickly clearing an FPR to zero presently requires Load.
 
 **Notes and Observations**: