From: Luke Kenneth Casson Leighton Date: Sun, 5 Jul 2020 12:56:44 +0000 (+0100) Subject: check spr1 in test spr compunit X-Git-Tag: div_pipeline~162^2~61 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67e38b7c060ac8817f8522fddefaa4382f290292;p=soc.git check spr1 in test spr compunit --- diff --git a/src/soc/fu/compunits/test/test_spr_compunit.py b/src/soc/fu/compunits/test/test_spr_compunit.py index bcc7b851..5fa58b9e 100644 --- a/src/soc/fu/compunits/test/test_spr_compunit.py +++ b/src/soc/fu/compunits/test/test_spr_compunit.py @@ -42,11 +42,13 @@ class SPRTestRunner(TestRunner): yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2) ALUHelpers.check_xer_ov(self, res, sim_o, code) ALUHelpers.check_xer_ca(self, res, sim_o, code) ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_fast_spr1(self, res, sim_o, code) + ALUHelpers.check_slow_spr1(self, res, sim_o, code) ALUHelpers.check_xer_so(self, res, sim_o, code)