From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 15 Feb 2014 12:16:08 +0000 (+0100)
Subject: Fixed opt_const handling of double invert with non-1 output width
X-Git-Tag: yosys-0.2.0~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67effc9f5bc82b45ff163bfefea53c40d2c8819a;p=yosys.git

Fixed opt_const handling of double invert with non-1 output width
---

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 34d1a69c1..f611d7211 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -108,7 +108,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 #define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
 #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_))
 
-		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") &&
+		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 &&
 				invert_map.count(assign_map(cell->connections["\\A"])) != 0) {
 			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"])));
 			goto next_cell;