From: Ali Saidi <saidi@eecs.umich.edu>
Date: Sun, 12 Feb 2012 23:18:53 +0000 (-0600)
Subject: configs: fix minor config bugs posted on the mailing list
X-Git-Tag: stable_2012_06_28~237
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67f16a48fb818a8409420fc6b72a176e1854b8e0;p=gem5.git

configs: fix minor config bugs posted on the mailing list
---

diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index d4607dc55..d881fafb0 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -112,7 +112,7 @@ Benchmarks = {
 
     'MutexTest':        [SysConfig('mutex-test.rcS', '128MB')],
     'ArmAndroid':       [SysConfig('null.rcS', '256MB',
-                     'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img)')],
+                     'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img')],
     'bbench':           [SysConfig('bbench.rcS', '256MB',
                             'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img')]
 }
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 8a9b815e6..23e986b09 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -210,6 +210,7 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 system.physmem.port = system.membus.port
 system.l2.cpu_side = system.toL2bus.port
 system.l2.mem_side = system.membus.port
+system.system_port = system.membus.port
 
 # ----------------------
 # Connect the L2 cache and clusters together