From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Feb 2022 13:54:43 +0000 (+0000)
Subject: add missing reset-HI values to cas_n, cs_n, we_n and act_n
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67f6ece9bb6a04b8c087527899c81daa895e07b8;p=gram.git

add missing reset-HI values to cas_n, cs_n, we_n and act_n
---

diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index d76b764..814ad1b 100644
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -43,6 +43,11 @@ class Interface:
                                          nranks, databits),
                        name=name)
             self.phases += [p]
+            # set all logic-inverted x_n signal resets to on at power-up
+            p.cas.reset = 1
+            p.cs_n.reset = -1
+            p.we.reset = 1
+            p.act.reset = 1
 
     def connect(self, target):
         if not isinstance(target, Interface):