From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 Apr 2022 13:02:01 +0000 (+0100)
Subject: shuffle addresses around a bit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=67f8d6a58677b77d11e900dea916ac34c77c8b7a;p=ls2.git

shuffle addresses around a bit
* firmware ROM is at 0xff00_0000
* DRAM is at 0x0000_0000
* for no real reason if DRAM is not present at 0x0 an SRAM is added
* set the default coldboot compile-start address at 0xff00_0000
---

diff --git a/coldboot/Makefile b/coldboot/Makefile
index 1fb2422..d4ccbec 100644
--- a/coldboot/Makefile
+++ b/coldboot/Makefile
@@ -12,11 +12,12 @@ SHORT_TIMER_MULT = 1000
 #LONG_TIMER_MULT = 1
 #SHORT_TIMER_MULT = 1
 
-# SPI boot address 0x1000_0000, main SRAM boot would be 0x0000_0000
+# SPI boot address 0xf000_0000, main SRAM boot would be 0x0000_0000
 # but remember to recompile external_core_top.v with a matching
 # --pc_reset=0xNNNNNNNN
-# BOOT_INIT_BASE ?= 0x10000000
-BOOT_INIT_BASE ?= 0x0
+# BOOT_INIT_BASE ?= 0xf0000000 # at QSPI address
+BOOT_INIT_BASE ?= 0xff000000   # at ROM hi address (with coldboot firmware)
+# BOOT_INIT_BASE ?= 0x0        # start at zero (usual)
 
 LIBGRAMDIR = ../libgram
 LIBGRAMINC = ../libgram/include
diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 0970930..777695c 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -427,11 +427,11 @@ for (i=0;i<1000;i++) {
         (ftr & SYS_REG_INFO_HAS_DRAM) &&
         (failcnt == 0))
     {
-        // identify ELF, copy if present, and get the offset/addr
+        // identify ELF, copy if present, and get the start address
         unsigned long faddr = copy_flash(spi_offs);
         if (faddr != -1ul) {
-            // jump to offset/addr relative to DRAM base
-            return DRAM_BASE + faddr;
+            // jump to absolute address
+            return faddr;
         }
     }
 
diff --git a/src/ls2.py b/src/ls2.py
index 94adc8b..c4c63bc 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -303,8 +303,9 @@ class DDR3SoC(SoC, Elaboratable):
             # CPU interrupt controller
             self.intc = GenericInterruptController(width=len(self.cpu.irq))
 
-        # SRAM (but actually a ROM, for firmware), at address 0x0
+        # SRAM (but actually a ROM, for firmware)
         if fw_addr is not None:
+            print ("fw at address %x" % fw_addr)
             sram_width = 32
             self.bootmem = SRAMPeripheral(size=0x8000, data_width=sram_width,
                                       writable=True)
@@ -321,7 +322,8 @@ class DDR3SoC(SoC, Elaboratable):
         dram_offset = ddr_addr if (ddr_pins is not None) else None
         self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq,
                                       has_uart=(uart_pins is not None),
-                                      spi_offset=spi_offset)
+                                      spi_offset=spi_offset,
+                                      dram_addr=dram_offset)
         self._decoder.add(self.syscon.bus, addr=0xc0000000) # at 0xc000_0000
 
         if False:
@@ -397,6 +399,15 @@ class DDR3SoC(SoC, Elaboratable):
                 self.drambone = drs(drambone)
             self._decoder.add(self.drambone.bus, addr=ddr_addr)
 
+            # additional SRAM at address if DRAM is not also at 0x0
+            # (TODO, check Flash, and HyperRAM as well)
+            if ddr_addr != 0x0:
+                sram_width = 32
+                self.bootmem = SRAMPeripheral(size=0x8000,
+                                          data_width=sram_width,
+                                          writable=True)
+                self._decoder.add(self.bootmem.bus, addr=0x0) # RAM at 0x0
+
         # SPI controller
         if spi_0_pins is not None and fpga in ['sim',
                                              'isim',
@@ -661,7 +672,7 @@ def build_platform(fpga, firmware):
     # select a firmware address
     fw_addr = None
     if firmware is not None:
-        fw_addr = 0x0000_0000
+        fw_addr = 0xff00_0000 # firmware at HI address, now
 
     print ("fpga", fpga, "firmware", firmware)
 
@@ -799,9 +810,9 @@ def build_platform(fpga, firmware):
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
                   # check microwatt_soc.h for these
-                  ddrphy_addr=0xff000000,   # DRAM_INIT_BASE firmware base
+                  ddrphy_addr=0xfff00000,   # DRAM_INIT_BASE, PHY address
                   dramcore_addr=0xc8000000, # DRAM_CTRL_BASE
-                  ddr_addr=0x40000000,      # DRAM_BASE
+                  ddr_addr=0x00000000,      # DRAM_BASE
                   spi0_addr=0xf0000000,     # SPI0_BASE
                   spi0_cfg_addr=0xc0003000, # SPI0_CTRL_BASE
                   eth0_cfg_addr=0xc0004000, # ETH0_CTRL_BASE (4k)