From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 12:46:26 +0000 (+0000)
Subject: woo! got FPADD pipeline to work
X-Git-Tag: ls180-24jan2020~1437
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6808bbc839d09e7f90e4f25f631bec163ad4efb2;p=ieee754fpu.git

woo! got FPADD pipeline to work

required some m.d.sync to be converted to m.d.comb in multi-stage chains
state-based version did not care but pipeline did
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 71d2b5dc..3fa5b445 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -464,7 +464,7 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
         FPState.__init__(self, "special_cases")
         self.smod = FPAddSpecialCasesMod(width, id_wid)
         self.dmod = FPAddDeNormMod(width, id_wid)
-        UnbufferedPipeline.__init__(self, self)
+        UnbufferedPipeline.__init__(self, self) # pipe is its own stage
         self.o = self.ospec()
 
     def ispec(self):
@@ -488,7 +488,7 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
         #m.d.sync += out_z.mid.eq(self.smod.o.mid)  # (and mid)
 
         # out_do_z=False
-        m.d.sync += self.o.eq(self.dmod.o)
+        m.d.comb += self.o.eq(self.dmod.o)
 
     def process(self, i):
         return self.o
@@ -775,7 +775,7 @@ class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
         FPState.__init__(self, "align")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self)
+        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
         self.a1o = self.ospec()
 
     def ispec(self):
@@ -797,7 +797,7 @@ class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
         chain = StageChain([mod, a0mod, a1mod])
         chain.setup(m, i)
 
-        m.d.sync += self.a1o.eq(a1mod.o)
+        m.d.comb += self.a1o.eq(a1mod.o)
 
     def process(self, i):
         return self.a1o
@@ -1339,7 +1339,7 @@ class FPNormToPack(FPState, UnbufferedPipeline):
         FPState.__init__(self, "normalise_1")
         self.id_wid = id_wid
         self.width = width
-        UnbufferedPipeline.__init__(self, self)
+        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
 
     def ispec(self):
         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
@@ -1360,8 +1360,8 @@ class FPNormToPack(FPState, UnbufferedPipeline):
         chain.setup(m, i)
         self.out_z = pmod.ospec()
 
-        m.d.sync += self.out_z.mid.eq(pmod.o.mid)
-        m.d.sync += self.out_z.z.eq(pmod.o.z) # outputs packed result
+        m.d.comb += self.out_z.mid.eq(pmod.o.mid)
+        m.d.comb += self.out_z.z.eq(pmod.o.z) # outputs packed result
 
     def process(self, i):
         return self.out_z
diff --git a/src/add/test_fpadd_pipe.py b/src/add/test_fpadd_pipe.py
index 32bf072d..4bac9279 100644
--- a/src/add/test_fpadd_pipe.py
+++ b/src/add/test_fpadd_pipe.py
@@ -20,7 +20,7 @@ class InputTest:
         self.dut = dut
         self.di = {}
         self.do = {}
-        self.tlen = 4
+        self.tlen = 10
         self.width = 32
         for mid in range(dut.num_rows):
             self.di[mid] = {}
@@ -28,6 +28,8 @@ class InputTest:
             for i in range(self.tlen):
                 op1 = randint(0, (1<<self.width)-1)
                 op2 = randint(0, (1<<self.width)-1)
+                #op1 = 0x40900000
+                #op2 = 0x40200000
                 res = Float32(op1) + Float32(op2)
                 self.di[mid][i] = (op1, op2)
                 self.do[mid].append(res.bits)