From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 18:38:08 +0000 (+0000)
Subject: add $Display of oper_r.msr in LDSTCompUnit
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6824daf09db467cf4fb6cc9a53134e5b72ef87f9;p=soc.git

add $Display of oper_r.msr in LDSTCompUnit
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 61f0d3cf..2baedc29 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -533,14 +533,15 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
         with m.If(op_is_dcbz):
-            sync += Display("MMUTEST.DCBZ: EA from adder %i",addr_r)
+            sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r)
 
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         comb += self.exc_o.eq(pi.exc_o)  # exception occurred
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
         # connect MSR.PR for priv/virt operation
         comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
-        comb += Display("MMUTEST: pi.msr_pr=%i",oper_r.msr[MSR.PR])
+        comb += Display("LDSTCompUnit: oper_r.msr %x pi.msr_pr=%x",
+                                      oper_r.msr, oper_r.msr[MSR.PR])
 
         # byte-reverse on LD
         revnorev = Signal(64, reset_less=True)