From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 17:17:46 +0000 (+0000)
Subject: dewildcardify units
X-Git-Tag: div_pipeline~1708
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68260ea71df320e3053fecf732f16b491d27d726;p=soc.git

dewildcardify units
---

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 45d74872..b140aa20 100644
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -1,8 +1,8 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Record
 from nmigen.utils import log2_int
 
-from ..cache import *
-from ..wishbone import *
+from ..cache import L1Cache
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"]
diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 0fe92f0c..ac2a0426 100644
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -1,10 +1,10 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Record, Cat
 from nmigen.utils import log2_int
 from nmigen.lib.fifo import SyncFIFO
 
-from ..cache import *
+from ..cache import L1Cache
 from ..isa import Funct3
-from ..wishbone import *
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["DataSelector", "LoadStoreUnitInterface", "BareLoadStoreUnit", "CachedLoadStoreUnit"]
diff --git a/src/soc/minerva/units/logic.py b/src/soc/minerva/units/logic.py
index fe96ede1..143cd7f8 100644
--- a/src/soc/minerva/units/logic.py
+++ b/src/soc/minerva/units/logic.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 
 from ..isa import Funct3
 
diff --git a/src/soc/minerva/units/multiplier.py b/src/soc/minerva/units/multiplier.py
index 80e7a0c0..c79d987e 100644
--- a/src/soc/minerva/units/multiplier.py
+++ b/src/soc/minerva/units/multiplier.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Cat, Mux
 
 from ..isa import Funct3
 
diff --git a/src/soc/minerva/units/predict.py b/src/soc/minerva/units/predict.py
index f5617903..b95deaaa 100644
--- a/src/soc/minerva/units/predict.py
+++ b/src/soc/minerva/units/predict.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 
 
 __all__ = ["BranchPredictor"]
diff --git a/src/soc/minerva/units/rvficon.py b/src/soc/minerva/units/rvficon.py
index 6442ef51..266fd12a 100644
--- a/src/soc/minerva/units/rvficon.py
+++ b/src/soc/minerva/units/rvficon.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
+from nmigen.hdl.rec import DIR_FANOUT
 
-from ..isa import *
-from ..wishbone import *
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["rvfi_layout", "RVFIController"]
diff --git a/src/soc/minerva/units/shifter.py b/src/soc/minerva/units/shifter.py
index c6a2ed0f..4ecd9fc0 100644
--- a/src/soc/minerva/units/shifter.py
+++ b/src/soc/minerva/units/shifter.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Mux, Repl, Cat
 
 
 __all__ = ["Shifter"]
diff --git a/src/soc/minerva/units/trigger.py b/src/soc/minerva/units/trigger.py
index 147c0cd0..203b6081 100644
--- a/src/soc/minerva/units/trigger.py
+++ b/src/soc/minerva/units/trigger.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
-from ..csr import *
-from ..isa import *
+from ..csr import AutoCSR, CSR
+from ..isa import flat_layout, tdata1_layout
 
 
 __all__ = ["TriggerUnit"]