From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 18:33:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2314
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=682c6b74227fea89dd39c4788dfd8d095743d997;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 9d3f89a1a..d2586208e 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -261,7 +261,8 @@ The question then becomes: with all the duplication of arithmetic
 operations just to make the registers scalar or vector, why not
 leverage the *existing* Scalar ISA with some sort of "context"
 or prefix that augments its behaviour? Make "Scalar instruction"
-synonymous with "Scalar instruction" and through contextual
+synonymous with "Vector Element instruction" and through nothing
+more than contextual
 augmentation the Scalar ISA *becomes* the Vector ISA.
 Then, by not having to have any Vector instructions at all,
 the Instruction Decode