From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 Nov 2019 20:59:34 +0000 (-0800)
Subject: Fix debug
X-Git-Tag: working-ls180~881^2^2~134
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6831510f5b436ddf05b8a1cb30b52be67f865de0;p=yosys.git

Fix debug
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2409f3d91..193103747 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -347,10 +347,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		log_assert(!design->module(ID($__abc9__)));
 		{
 			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-			reader.parse_xaiger();
+			reader.parse_xaiger(box_lookup);
 		}
 		ifs.close();
-		Pass::call(design, stringf("write_verilog -noexpr -norename"));
+		Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
 		design->remove(design->module(ID($__abc9__)));
 #endif
 
@@ -421,7 +421,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		ifs.close();
 
 #if 0
-		Pass::call(design, stringf("write_verilog -noexpr -norename"));
+		Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
 #endif
 
 		log_header(design, "Re-integrating ABC9 results.\n");