From: Luke Kenneth Casson Leighton Date: Tue, 28 May 2019 04:55:15 +0000 (+0100) Subject: reword multiplier section X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68573c2135c91300729b9a195c1108098bd2b965;p=crowdsupply.git reword multiplier section --- diff --git a/updates/018_2019may27_nlnet_grant_approved.mdwn b/updates/018_2019may27_nlnet_grant_approved.mdwn index fcf3e56..9e35bbd 100644 --- a/updates/018_2019may27_nlnet_grant_approved.mdwn +++ b/updates/018_2019may27_nlnet_grant_approved.mdwn @@ -75,10 +75,10 @@ Adder and Multiplier Unit. Given that we are doing a Vector Processing front-end onto SIMD back-end operations, it makes sense to save gates by allowing the ADD and MUL units to be able to optionally handle a batch of 8-bit operations, or half the number of 16-bit operations, or a quarter -of the number of 32-bit operations or just one 64-bit operation. -In this way, a lot less gates are required than if they were separate units. -The unit tests demonstrate that the code that Jacob has written provide -RISC-V mul, mulh, mulhu and mulhsu functionality. +of the number of 32-bit operations or one eigth of the number of64-bit +operations. In this way, a lot less gates are required than if they +were separate units. The unit tests demonstrate that the code that Jacob +has written provide RISC-V mul, mulh, mulhu and mulhsu functionality. The augmented 6600 Scoreboard took literally six weeks to correctly implement Read-after-Write and Write-after-Read hazards. It required extraordinary