From: Andrew Waterman Date: Tue, 1 Mar 2011 21:12:31 +0000 (-0800) Subject: [xcc,sim] branches are pc-relative (not pc+4) again X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68591c3c451dca19d4751eb62861367f2a3e58b5;p=riscv-isa-sim.git [xcc,sim] branches are pc-relative (not pc+4) again --- diff --git a/riscv/decode.h b/riscv/decode.h index 40b8b5e..d0b92dd 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -178,8 +178,8 @@ private: #define SHAMT (insn.itype.imm12 & 0x3F) #define SHAMTW (insn.itype.imm12 & 0x1F) #define TARGET insn.jtype.target -#define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS)) -#define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS)) +#define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS)) +#define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS)) #define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \ ((fsr & FSR_RD) >> FSR_RD_SHIFT))