From: H.J. Lu <hjl.tools@gmail.com>
Date: Fri, 14 Feb 2020 13:40:19 +0000 (-0800)
Subject: Remove Intel syntax comments on movsx and movzx
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6867aac05b9677ff9e0f388d7c10d3bc38fc524b;p=binutils-gdb.git

Remove Intel syntax comments on movsx and movzx

Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel
syntax comments on movsx and movzx to avoid confusing other readers.

	* i386-opc.tbl (movsx): Remove Intel syntax comments.
	(movzx): Likewise.
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a53d646e422..103c508be04 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl (movsx): Remove Intel syntax comments.
+	(movzx): Likewise.
+
 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 
 	PR gas/25438
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 6eb7238589e..01cf61a6247 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -132,7 +132,6 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf
 movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
 movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
 movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
-// Intel Syntax next 2 insns
 movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
 movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
@@ -142,8 +141,8 @@ movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 // Move with zero extend.
 movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
-// Intel Syntax next insn (the 64-bit variant is not particulary
-// useful since the zero extend 32->64 is implicit, but we can encode them).
+// The 64-bit variant is not particularly useful since the zero extend
+// 32->64 is implicit, but we can encode them.
 movzx, 2, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // Push instructions.