From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 Nov 2019 23:42:07 +0000 (-0800)
Subject: Do not sigmap keep bits inside write_xaiger
X-Git-Tag: working-ls180~945^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68717dd03b5a0bfff470cfbc004a43dd431f9236;p=yosys.git

Do not sigmap keep bits inside write_xaiger
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 85136118a..97fec9376 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -168,7 +168,7 @@ struct XAigerWriter
 				}
 
 				if (keep)
-					keep_bits.insert(bit);
+					keep_bits.insert(wirebit);
 
 				if (wire->port_input || keep) {
 					if (bit != wirebit)