From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 17:00:50 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
X-Git-Tag: working-ls180~1097^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6872805a3eb738a0a5921b232022abfd507cebb8;p=yosys.git

Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
---

6872805a3eb738a0a5921b232022abfd507cebb8
diff --cc CHANGELOG
index bd4cd1b1b,ca42df71e..b68f0bbfa
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -19,11 -23,10 +23,15 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Added automatic gzip compression (based on filename extension) for backends
      - Improve attribute and parameter encoding in JSON to avoid ambiguities between
        bit vectors and strings containing [01xz]*
 +    - Added "clkbufmap" pass
 +    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
 +    - Added "synth_xilinx -ise" (experimental)
 +    - Added "synth_xilinx -iopad"
 +    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
+     - Improvements in pmgen: subpattern and recursive matches
+     - Added "opt_share" pass, run as part of "opt -full"
+     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
+     - Removed "ice40_unlut"
  
  Yosys 0.8 .. Yosys 0.8-dev
  --------------------------
diff --cc techlibs/xilinx/cells_sim.v
index 27511a05f,bec9ea1a0..26df5bc93
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -304,12 -295,12 +310,12 @@@ module FDPE_1 (output reg Q, (* clkbuf_
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
- (* abc_box_id = 5, abc_scc_break="D,WE" *)
+ (* abc_box_id = 5 *)
  module RAM32X1D (
    output DPO, SPO,
-   (* clkbuf_sink *)
-   input  WCLK,
-   input  D, WE,
+   (* abc_scc_break *) input D,
 -  input  WCLK,
++  (* clkbuf_sink *) input  WCLK,
+   (* abc_scc_break *) input WE,
    input  A0, A1, A2, A3, A4,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
  );
@@@ -324,12 -315,12 +330,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
- (* abc_box_id = 6, abc_scc_break="D,WE" *)
+ (* abc_box_id = 6 *)
  module RAM64X1D (
    output DPO, SPO,
-   (* clkbuf_sink *)
-   input  WCLK,
-   input  D, WE,
+   (* abc_scc_break *) input D,
 -  input  WCLK,
++  (* clkbuf_sink *) input  WCLK,
+   (* abc_scc_break *) input WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
  );
@@@ -344,12 -335,12 +350,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
- (* abc_box_id = 7, abc_scc_break="D,WE" *)
+ (* abc_box_id = 7 *)
  module RAM128X1D (
    output       DPO, SPO,
-   input        D, WE,
-   (* clkbuf_sink *)
-   input        WCLK,
+   (* abc_scc_break *) input D,
 -  input        WCLK,
++  (* clkbuf_sink *) input WCLK,
+   (* abc_scc_break *) input WE,
    input  [6:0] A, DPRA
  );
    parameter INIT = 128'h0;
diff --cc techlibs/xilinx/synth_xilinx.cc
index 4069094a6,7ba67409b..00849ad00
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -63,17 -63,14 +63,17 @@@ struct SynthXilinxPass : public ScriptP
  		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  		log("        (this feature is experimental and incomplete)\n");
  		log("\n");
 +		log("    -ise\n");
 +		log("        generate an output netlist suitable for ISE (enables -iopad)\n");
 +		log("\n");
  		log("    -nobram\n");
- 		log("        disable inference of block rams\n");
+ 		log("        do not use block RAM cells in output netlist\n");
  		log("\n");
- 		log("    -nodram\n");
- 		log("        disable inference of distributed rams\n");
+ 		log("    -nolutram\n");
+ 		log("        do not use distributed RAM cells in output netlist\n");
  		log("\n");
  		log("    -nosrl\n");
- 		log("        disable inference of shift registers\n");
+ 		log("        do not use distributed SRL cells in output netlist\n");
  		log("\n");
  		log("    -nocarry\n");
  		log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@@@ -116,7 -104,7 +116,7 @@@
  	}
  
  	std::string top_opt, edif_file, blif_file, family;
- 	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 -	bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
++	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
  	int widemux;
  
  	void clear_flags() YS_OVERRIDE
@@@ -128,13 -116,9 +128,13 @@@
  		flatten = false;
  		retime = false;
  		vpr = false;
 +		ise = false;
 +		iopad = false;
 +		noiopad = false;
 +		noclkbuf = false;
  		nocarry = false;
  		nobram = false;
- 		nodram = false;
+ 		nolutram = false;
  		nosrl = false;
  		nocarry = false;
  		nowidelut = false;