From: lkcl <lkcl@web>
Date: Thu, 23 Nov 2023 17:39:34 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=687bf18d05231f055235df2afec96ba1013697e6;p=libreriscv.git

---

diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn
index 40b4c8fc5..36ecc7d4b 100644
--- a/nlnet_2023_simplev_riscv.mdwn
+++ b/nlnet_2023_simplev_riscv.mdwn
@@ -35,7 +35,7 @@ RISC-V is the largest open-source global community for microprocessor architectu
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
+A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of the Power ISA. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
 they include recently:
 
 * <https://libre-soc.org/nlnet_2022_opf_isa_wg/> - improving SVP64