From: lkcl <lkcl@web>
Date: Thu, 13 May 2021 16:07:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~923
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=688479b2dca63e676884568f5db9885c0541562c;p=libreriscv.git

---

diff --git a/conferences/ics2021.mdwn b/conferences/ics2021.mdwn
index 84d8f6f11..fc6c38dc4 100644
--- a/conferences/ics2021.mdwn
+++ b/conferences/ics2021.mdwn
@@ -43,9 +43,10 @@ Loops from DSPs and Intel MMX, the end result is something entirely new.
 This talk will go through the development process of SVP64 and explain
 some of the innovative Vectorisation concepts that have never been seen 
 before in any commercial or academic Vector ISA, including
-Twin-Predication and "Post-result" predication, and how these will
-benefit Supercomputing performance and decrease power consumption,
-by reducing I-Cache usage.
+Twin-Predication and Condition Register "Post-result" predication,
+and how these will benefit Supercomputing performance and decrease
+power consumption, most notably by reducing program size and
+thus I-Cache usage whilst still maintaining high data throughput.
 
 ## Comprehensive life-cycle of mixed testing: HDL to gates