From: lkcl <lkcl@web>
Date: Thu, 20 Apr 2023 11:24:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=688b99a3cb97c5270e78103790813e78ed3fcce1;p=libreriscv.git

---

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index ec7f90244..a06384935 100644
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -72,21 +72,28 @@ The following seven new areas are defined within Primary Opcode 9 (EXT009)
 as a new 64-bit encoding space, alongside Primary Opcode 1
 (EXT1xx).
 
-| 0-5 | 6 | 7 | 8-31  | 32| Description                        |
-|-----|---|---|-------|---|------------------------------------|
-| PO  | 0 | x | xxxx  | 0 | `RESERVED2` (57-bit) |
-| PO  | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
-| PO  | 0 | 0 | 0000  | 1 | Scalar EXT232-263               |
-| PO  | 0 | 1 | nnnn  | 1 | SVP64:EXT232-263     |
-| PO  | 1 | 0 | 0000  | x | `RESERVED1` (32-bit) |
-| PO  | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
-| PO  | 1 | 1 | nnnn  | n | SVP64:EXT000-063       |
+| 0-5 | 6 | 7 | 8-31  | 32|33-63|Description                        |
+|-----|---|---|-------|---|-----|-----------------------------------|
+| PO9 | 0 | x | xxxx  | 0 | xxxx|  `RESERVED2` (57-bit) |
+| PO9 | 0 | 0 | !zero | 1 | DWd | SVP64Single:EXT232-263, or `RESERVED3` |
+| PO9 | 0 | 0 | 0000  | 1 | DWd | Scalar EXT232-263               |
+| PO9 | 0 | 1 | nnnn  | 1 | DWd | SVP64:EXT232-263     |
+| PO9 | 1 | 0 | 0000  | x | xxxx| `RESERVED1` (32-bit) |
+| PO9 | 1 | 0 | !zero | n | DWd | SVP64Single:EXT000-063 or `RESERVED4` |
+| PO9 | 1 | 1 | nnnn  | n | DWd | SVP64:EXT000-063       |
+
+Key:
+
+* **x** - a `RESERVED` encoding. Illegal Instruction Trap must be raised
+* **n** - a specification-defined value
+* **!zero** - a non-zero specification-defined value
+* **DWd** - "Defined Word" as explained in Book I Section 1.6 (Public v3.1 p11)
 
 Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
 it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
 for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
 prohibition allows SVP64Single to share its Encoding space with Scalar
-Ext232-263 and Scalar EXT300-363.
+EXT232-263 and Scalar EXT300-363.
 
 Also that RESERVED1 and 2 are candidates for future Major opcode
 areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas