From: colepoirier <colepoirier@gmail.com>
Date: Sat, 20 Jun 2020 01:30:54 +0000 (-0700)
Subject: Add code, commented-out, for TRAP so as to not break test_caller.py
X-Git-Tag: div_pipeline~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6891172f1bffde3f2b322a9151c21964b8f6f35d;p=soc.git

Add code, commented-out, for TRAP so as to not break test_caller.py
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7bf411fd..b3b2c171 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -297,6 +297,10 @@ class ISACaller:
 
     def TRAP(self, trap_addr=0x700):
         print ("TRAP: TODO")
+        #self.namespace['NIA'] = trap_addr
+        #self.SRR0 = self.namespace['CIA'] + 4
+        #self.SRR1 = self.namespace['MSR']
+        #self.namespace['MSR'][45] = 1
         # store CIA(+4?) in SRR0, set NIA to 0x700
         # store MSR in SRR1, set MSR to um errr something, have to check spec