From: Jan Beulich Date: Fri, 16 Dec 2022 08:00:23 +0000 (+0100) Subject: x86: change representation of extension opcode X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=689933867ad45487751a6bb411e69cd91ef24990;p=binutils-gdb.git x86: change representation of extension opcode Having a "None" field in the vast majority of entries is needlessly cluttering the overall table. Instead of this being a separate field, use a representation matching that of Intel SDM and AMD PM for the main use of the field: Append the value after a / as the separator. --- diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5f68f933f15..101f6860ce2 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1299,8 +1299,10 @@ output_i386_opcode (FILE *table, const char *name, char *str, /* Find base_opcode. */ base_opcode = next_field (str, ',', &str, last); - /* Find extension_opcode. */ - extension_opcode = next_field (str, ',', &str, last); + /* Find extension_opcode, if any. */ + extension_opcode = strchr (base_opcode, '/'); + if (extension_opcode) + *extension_opcode++ = '\0'; /* Find cpu_flags. */ cpu_flags = next_field (str, ',', &str, last); @@ -1385,7 +1387,8 @@ output_i386_opcode (FILE *table, const char *name, char *str, filename, lineno, name, 2 * length, opcode); fprintf (table, " { \"%s\", 0x%0*llx%s, %lu, %s,\n", - name, 2 * (int)length, opcode, end, i, extension_opcode); + name, 2 * (int)length, opcode, end, i, + extension_opcode ? extension_opcode : "None"); process_i386_opcode_modifier (table, opcode_modifier, space, prefix, operand_types, lineno); diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 20ae7e8173c..44a8ca33fed 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -20,7 +20,6 @@ #define OPCODE_I386_H #include "i386-opc.h" -#undef None // When necessary lines can be split in a non-standard way, by placing a // trailing + on a to-be-continued line. This is intended mainly for non-insn @@ -142,723 +141,723 @@ ### MARKER ### // Move instructions. -mov, 0xa0, None, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } -mov, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } -movabs, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } -mov, 0x88, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +mov, 0xa0, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } +mov, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +movabs, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +mov, 0x88, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } // In the 64bit mode the short form mov immediate is redefined to have // 64bit value. -mov, 0xb0, None, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } -mov, 0xc6, 0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -mov, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } -movabs, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } +mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } +mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +mov, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } +movabs, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } // The segment register moves accept WordReg so that a segment register // can be copied to a 32 bit register, and vice versa, without using a // size prefix. When moving to a 32 bit register, the upper 16 bits // are set to an implementation defined value (on the Pentium Pro, the // implementation defined value is zero). -mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } -mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|Unspecified|BaseIndex } -mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } +mov, 0x8c, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } +mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|Unspecified|BaseIndex } +mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } // Move to/from control debug registers. In the 16 or 32bit modes // they are 32bit. In the 64bit mode they are 64bit. -mov, 0xf20, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } -mov, 0xf20, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } -mov, 0xf21, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } -mov, 0xf21, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } -mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } +mov, 0xf20, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } +mov, 0xf20, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } +mov, 0xf21, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } +mov, 0xf21, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } +mov, 0xf24, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } // Move after swapping the bytes -movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movbe, 0x0f38f0, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Move with sign extend. -movsb, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsw, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movsl, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 } -movsx, 0xfbe, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -movsxd, 0x63, None, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -movsxd, 0x63, None, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } -movsxd, 0x63, None, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } +movsb, 0xfbe, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsw, 0xfbf, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } +movsl, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 } +movsx, 0xfbe, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +movsxd, 0x63, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +movsxd, 0x63, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } +movsxd, 0x63, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } // Move with zero extend. -movzb, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movzw, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } +movzb, 0xfb6, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzw, 0xfb7, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } // The 64-bit variant is not particularly useful since the zero extend // 32->64 is implicit, but we can encode them. -movzx, 0xfb6, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 0xfb6, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Push instructions. -push, 0x50, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -push, 0xff, 6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } -push, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } -push, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } -push, 0x6, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } +push, 0x50, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +push, 0xff/6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +push, 0x6a, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } +push, 0x68, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } +push, 0x6, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -push, 0x50, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } -push, 0xff, 6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } -push, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } -push, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } -push, 0xfa0, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } +push, 0x50, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +push, 0xff/6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +push, 0x6a, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } +push, 0x68, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } +push, 0xfa0, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } -pusha, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +pusha, 0x60, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} // Pop instructions. -pop, 0x58, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -pop, 0x8f, 0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } -pop, 0x7, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } +pop, 0x58, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +pop, 0x8f/0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +pop, 0x7, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -pop, 0x58, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } -pop, 0x8f, 0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } -pop, 0xfa1, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } +pop, 0x58, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +pop, 0x8f/0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +pop, 0xfa1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } -popa, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +popa, 0x61, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} // Exchange instructions. // xchg commutes: we allow both operand orders. // In the 64bit code, xchg rax, rax is reused for new nop instruction. -xchg, 0x90, None, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } -xchg, 0x86, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } +xchg, 0x90, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } +xchg, 0x86, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } // In/out from ports. -in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword } -in, 0xec, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword } -in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8 } -in, 0xec, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg } -out, 0xe6, None, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 } -out, 0xee, None, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg } -out, 0xe6, None, 0, W|No_sSuf|No_qSuf, { Imm8 } -out, 0xee, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg } +in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword } +in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword } +in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8 } +in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg } +out, 0xe6, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 } +out, 0xee, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg } +out, 0xe6, 0, W|No_sSuf|No_qSuf, { Imm8 } +out, 0xee, 0, W|No_sSuf|No_qSuf, { InOutPortReg } // Load effective address. -lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 } +lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 } // Load segment registers from memory. -lds, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -les, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lfs, 0xfb4, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lfs, 0xfb4, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lgs, 0xfb5, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lgs, 0xfb5, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lss, 0xfb2, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lss, 0xfb2, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lds, 0xc5, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +les, 0xc4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lfs, 0xfb4, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lfs, 0xfb4, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lgs, 0xfb5, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lgs, 0xfb5, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lss, 0xfb2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lss, 0xfb2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Flags register instructions. -clc, 0xf8, None, 0, NoSuf, {} -cld, 0xfc, None, 0, NoSuf, {} -cli, 0xfa, None, 0, NoSuf, {} -clts, 0xf06, None, Cpu286, NoSuf, {} -cmc, 0xf5, None, 0, NoSuf, {} -lahf, 0x9f, None, 0, NoSuf, {} -sahf, 0x9e, None, 0, NoSuf, {} -pushf, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -pushf, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} -popf, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -popf, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} -stc, 0xf9, None, 0, NoSuf, {} -std, 0xfd, None, 0, NoSuf, {} -sti, 0xfb, None, 0, NoSuf, {} +clc, 0xf8, 0, NoSuf, {} +cld, 0xfc, 0, NoSuf, {} +cli, 0xfa, 0, NoSuf, {} +clts, 0xf06, Cpu286, NoSuf, {} +cmc, 0xf5, 0, NoSuf, {} +lahf, 0x9f, 0, NoSuf, {} +sahf, 0x9e, 0, NoSuf, {} +pushf, 0x9c, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +pushf, 0x9c, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +popf, 0x9d, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +popf, 0x9d, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +stc, 0xf9, 0, NoSuf, {} +std, 0xfd, 0, NoSuf, {} +sti, 0xfb, 0, NoSuf, {} // Arithmetic. -add, 0x0, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -add, 0x83, 0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -add, 0x4, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -add, 0x80, 0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -inc, 0x40, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -inc, 0xfe, 0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -sub, 0x28, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sub, 0x83, 5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -sub, 0x2c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -sub, 0x80, 5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -dec, 0x48, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -dec, 0xfe, 1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -sbb, 0x18, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sbb, 0x83, 3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -sbb, 0x1c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -sbb, 0x80, 3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -cmp, 0x38, None, 0, D|W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -cmp, 0x3c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -cmp, 0x80, 7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -test, 0x84, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -test, 0xa8, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -test, 0xf6, 0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -and, 0x20, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -and, 0x83, 4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -and, 0x24, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -and, 0x80, 4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -or, 0x8, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -or, 0x83, 1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -or, 0xc, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -or, 0x80, 1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -xor, 0x30, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -xor, 0x83, 6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -xor, 0x34, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -xor, 0x80, 6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x0, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +inc, 0x40, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sub, 0x28, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +dec, 0x48, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sbb, 0x18, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +cmp, 0x38, 0, D|W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +test, 0x84, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } +test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +and, 0x20, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +or, 0x8, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +xor, 0x30, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } // clr with 1 operand is really xor with 2 operands. -clr, 0x30, None, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } +clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } -adc, 0x10, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -adc, 0x83, 2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -adc, 0x14, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } -adc, 0x80, 2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x10, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -neg, 0xf6, 3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -not, 0xf6, 2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -aaa, 0x37, None, CpuNo64, NoSuf, {} -aas, 0x3f, None, CpuNo64, NoSuf, {} -daa, 0x27, None, CpuNo64, NoSuf, {} -das, 0x2f, None, CpuNo64, NoSuf, {} -aad, 0xd50a, None, CpuNo64, NoSuf, {} -aad, 0xd5, None, CpuNo64, NoSuf, { Imm8 } -aam, 0xd40a, None, CpuNo64, NoSuf, {} -aam, 0xd4, None, CpuNo64, NoSuf, { Imm8 } +aaa, 0x37, CpuNo64, NoSuf, {} +aas, 0x3f, CpuNo64, NoSuf, {} +daa, 0x27, CpuNo64, NoSuf, {} +das, 0x2f, CpuNo64, NoSuf, {} +aad, 0xd50a, CpuNo64, NoSuf, {} +aad, 0xd5, CpuNo64, NoSuf, { Imm8 } +aam, 0xd40a, CpuNo64, NoSuf, {} +aam, 0xd4, CpuNo64, NoSuf, { Imm8 } // Conversion insns. // Intel naming -cbw, 0x98, None, 0, Size16|NoSuf, {} -cwde, 0x98, None, Cpu386, Size32|NoSuf, {} -cdqe, 0x98, None, Cpu64, Size64|NoSuf, {} -cwd, 0x99, None, 0, Size16|NoSuf, {} -cdq, 0x99, None, Cpu386, Size32|NoSuf, {} -cqo, 0x99, None, Cpu64, Size64|NoSuf, {} +cbw, 0x98, 0, Size16|NoSuf, {} +cwde, 0x98, Cpu386, Size32|NoSuf, {} +cdqe, 0x98, Cpu64, Size64|NoSuf, {} +cwd, 0x99, 0, Size16|NoSuf, {} +cdq, 0x99, Cpu386, Size32|NoSuf, {} +cqo, 0x99, Cpu64, Size64|NoSuf, {} // AT&T naming -cbtw, 0x98, None, 0, Size16|NoSuf, {} -cwtl, 0x98, None, Cpu386, Size32|NoSuf, {} -cltq, 0x98, None, Cpu64, Size64|NoSuf, {} -cwtd, 0x99, None, 0, Size16|NoSuf, {} -cltd, 0x99, None, Cpu386, Size32|NoSuf, {} -cqto, 0x99, None, Cpu64, Size64|NoSuf, {} +cbtw, 0x98, 0, Size16|NoSuf, {} +cwtl, 0x98, Cpu386, Size32|NoSuf, {} +cltq, 0x98, Cpu64, Size64|NoSuf, {} +cwtd, 0x99, 0, Size16|NoSuf, {} +cltd, 0x99, Cpu386, Size32|NoSuf, {} +cqto, 0x99, Cpu64, Size64|NoSuf, {} // Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are // expanding 64-bit multiplies, and *cannot* be selected to accomplish // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) // These multiplies can only be selected with single operand forms. -mul, 0xf6, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -imul, 0xf6, 5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -imul, 0xfaf, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } -imul, 0x6b, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -imul, 0x69, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +imul, 0xfaf, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0x6b, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0x69, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // imul with 2 operands mimics imul with 3 by putting the register in // both i.rm.reg & i.rm.regmem fields. RegKludge enables this // transformation. -imul, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } -imul, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } - -div, 0xf6, 6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -div, 0xf6, 6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } -idiv, 0xf6, 7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -idiv, 0xf6, 7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } - -rol, 0xd0, 0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xc0, 0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xd2, 0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xd0, 0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -ror, 0xd0, 1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xc0, 1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xd2, 1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xd0, 1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -rcl, 0xd0, 2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcl, 0xc0, 2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcl, 0xd2, 2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcl, 0xd0, 2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -rcr, 0xd0, 3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcr, 0xc0, 3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcr, 0xd2, 3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcr, 0xd0, 3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -sal, 0xd0, 4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sal, 0xc0, 4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sal, 0xd2, 4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sal, 0xd0, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -shl, 0xd0, 4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shl, 0xc0, 4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shl, 0xd2, 4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shl, 0xd0, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -shr, 0xd0, 5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shr, 0xc0, 5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shr, 0xd2, 5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shr, 0xd0, 5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -sar, 0xd0, 7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sar, 0xc0, 7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sar, 0xd2, 7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sar, 0xd0, 7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } - -shld, 0xfa4, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } - -shrd, 0xfac, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +imul, 0x6b, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } +imul, 0x69, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } + +div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +div, 0xf6/6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +idiv, 0xf6/7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } + +rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xc0/0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xc0/1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xc0/2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xc0/3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sal, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xc0/5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xc0/7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +shld, 0xfa4, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } + +shrd, 0xfac, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // Control transfer instructions. -call, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } -call, 0xe8, None, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } -call, 0xe8, None, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } -call, 0xff, 2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } -call, 0xff, 2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } -call, 0xff, 2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } +call, 0xe8, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } +call, 0xe8, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } +call, 0xe8, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } +call, 0xff/2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } +call, 0xff/2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } +call, 0xff/2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } // Intel Syntax remaining call instances. -call, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } -call, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } -call, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } -lcall, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } -lcall, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } -lcall, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } - -jmp, 0xeb, None, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } -jmp, 0xeb, None, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } -jmp, 0xff, 4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } -jmp, 0xff, 4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } -jmp, 0xff, 4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } +call, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } +call, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } +lcall, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } +lcall, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } + +jmp, 0xeb, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } +jmp, 0xeb, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } +jmp, 0xff/4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } +jmp, 0xff/4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } +jmp, 0xff/4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } // Intel Syntax remaining jmp instances. -jmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } -jmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex } -jmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } -ljmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } -ljmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } -ljmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } - -ret, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } -ret, 0xc3, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } -ret, 0xc3, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } -lret, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf, {} -lret, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } +jmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex } +jmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } +ljmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } +ljmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } + +ret, 0xc3, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } +ret, 0xc3, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } +ret, 0xc3, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } +lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} +lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } // Intel Syntax. -retf, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf, {} -retf, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } +retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} +retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } -enter, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } -enter, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } -leave, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -leave, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +enter, 0xc8, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } +enter, 0xc8, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } +leave, 0xc9, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +leave, 0xc9, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} // Conditional jumps. -j, 0x7, None, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } +j, 0x7, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } // jcxz vs. jecxz is chosen on the basis of the address size prefix. -jcxz, 0xe3, None, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 } -jecxz, 0xe3, None, Cpu386, JumpByte|Size32|NoSuf, { Disp8 } -jrcxz, 0xe3, None, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } +jcxz, 0xe3, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 } +jecxz, 0xe3, Cpu386, JumpByte|Size32|NoSuf, { Disp8 } +jrcxz, 0xe3, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } // The loop instructions also use the address size prefix to select // %cx rather than %ecx for the loop count, so the `w' form of these // instructions emit an address size prefix rather than a data size // prefix. -loop, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loop, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopz, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopz, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loope, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loope, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopnz, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopnz, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopne, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopne, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loop, 0xe2, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loop, 0xe2, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopz, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopz, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loope, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loope, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopnz, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopnz, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopne, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopne, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } // Set byte on flag instructions. -set, 0xf9, 0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex } +set, 0xf9/0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex } // String manipulation. -cmps, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {} -cmps, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -scmp, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {} -scmp, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} -ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } -outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} -outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } -lods, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {} -lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } -slod, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {} -slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } -movs, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {} -movs, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -smov, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {} -smov, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -scas, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {} -scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } -ssca, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {} -ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } -stos, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {} -stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ssto, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {} -ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {} -xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex } +cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} +cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} +scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} +ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } +outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} +outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } +lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {} +lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +slod, 0xac, 0, W|No_sSuf|RepPrefixOk, {} +slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +movs, 0xa4, 0, W|No_sSuf|RepPrefixOk, {} +movs, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +smov, 0xa4, 0, W|No_sSuf|RepPrefixOk, {} +smov, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +scas, 0xae, 0, W|No_sSuf|RepPrefixOk, {} +scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +ssca, 0xae, 0, W|No_sSuf|RepPrefixOk, {} +ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +stos, 0xaa, 0, W|No_sSuf|RepPrefixOk, {} +stos, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +stos, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ssto, 0xaa, 0, W|No_sSuf|RepPrefixOk, {} +ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } +xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {} +xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex } // Bit manipulation. -bsf, 0xfbc, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -bsr, 0xfbd, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -bt, 0xfa3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bt, 0xfba, 4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btc, 0xfbb, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btc, 0xfba, 7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btr, 0xfb3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btr, 0xfba, 6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bts, 0xfab, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bsf, 0xfbc, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +bsr, 0xfbd, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +bt, 0xfa3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bt, 0xfba/4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btc, 0xfbb, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btc, 0xfba/7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btr, 0xfb3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btr, 0xfba/6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bts, 0xfab, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // Interrupts & op. sys insns. // See gas/config/tc-i386.c for conversion of 'int $3' into the special // int 3 insn. -int, 0xcd, None, 0, NoSuf, { Imm8 } -int1, 0xf1, None, 0, NoSuf, {} -int3, 0xcc, None, 0, NoSuf, {} -into, 0xce, None, CpuNo64, NoSuf, {} -iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf, {} +int, 0xcd, 0, NoSuf, { Imm8 } +int1, 0xf1, 0, NoSuf, {} +int3, 0xcc, 0, NoSuf, {} +into, 0xce, CpuNo64, NoSuf, {} +iret, 0xcf, 0, DefaultSize|No_bSuf|No_sSuf, {} // i386sl, i486sl, later 486, and Pentium. -rsm, 0xfaa, None, Cpu386, NoSuf, {} +rsm, 0xfaa, Cpu386, NoSuf, {} -bound, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } +bound, 0x62, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } -hlt, 0xf4, None, 0, NoSuf, {} +hlt, 0xf4, 0, NoSuf, {} -nop, 0xf1f, 0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +nop, 0xf1f/0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in // 32bit mode and "xchg %rax,%rax" in 64bit mode. -nop, 0x90, None, 0, NoSuf|RepPrefixOk, {} +nop, 0x90, 0, NoSuf|RepPrefixOk, {} // Protection control. -arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } -lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } - -sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -sgdt, 0xf01, 0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -sidt, 0xf01, 1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -sidt, 0xf01, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -sldt, 0xf00, 0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } -sldt, 0xf00, 0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -smsw, 0xf01, 4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 } -smsw, 0xf01, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -str, 0xf00, 1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } -str, 0xf00, 1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } - -verr, 0xf00, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -verw, 0xf00, 5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +arpl, 0x63, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } +lar, 0xf02, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } +lar, 0xf02, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lgdt, 0xf01/2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +lgdt, 0xf01/2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +lidt, 0xf01/3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +lidt, 0xf01/3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +lldt, 0xf00/2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +lmsw, 0xf01/6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +lsl, 0xf03, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } +lsl, 0xf03, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ltr, 0xf00/3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } + +sgdt, 0xf01/0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +sgdt, 0xf01/0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +sidt, 0xf01/1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +sidt, 0xf01/1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +sldt, 0xf00/0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +sldt, 0xf00/0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +smsw, 0xf01/4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 } +smsw, 0xf01/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +str, 0xf00/1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +str, 0xf00/1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } + +verr, 0xf00/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +verw, 0xf00/5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } // Floating point instructions. // load -fld, 0xd9c0, None, CpuFP, NoSuf, { FloatReg } -fld, 0xd9, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fld, 0xd9c0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fld, 0xd9c0, CpuFP, NoSuf, { FloatReg } +fld, 0xd9/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fld, 0xd9c0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } // Intel Syntax -fld, 0xdb, 5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } -fild, 0xdf, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fild, 0xdf, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fildll, 0xdf, 5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } -fldt, 0xdb, 5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbld, 0xdf, 4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fld, 0xdb/5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fild, 0xdf/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fild, 0xdf/5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fildll, 0xdf/5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fldt, 0xdb/5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } +fbld, 0xdf/4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } // store (no pop) -fst, 0xddd0, None, CpuFP, NoSuf, { FloatReg } -fst, 0xd9, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fst, 0xddd0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -fist, 0xdf, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fst, 0xddd0, CpuFP, NoSuf, { FloatReg } +fst, 0xd9/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fst, 0xddd0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fist, 0xdf/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } // store (with pop) -fstp, 0xddd8, None, CpuFP, NoSuf, { FloatReg } -fstp, 0xd9, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fstp, 0xddd8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fstp, 0xddd8, CpuFP, NoSuf, { FloatReg } +fstp, 0xd9/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fstp, 0xddd8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } // Intel Syntax -fstp, 0xdb, 7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } -fistp, 0xdf, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fistp, 0xdf, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fistpll, 0xdf, 7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } -fstpt, 0xdb, 7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbstp, 0xdf, 6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fstp, 0xdb/7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fistp, 0xdf/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fistp, 0xdf/7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fistpll, 0xdf/7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fstpt, 0xdb/7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } +fbstp, 0xdf/6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } // exchange %st with %st0 -fxch, 0xd9c8, None, CpuFP, NoSuf, { FloatReg } +fxch, 0xd9c8, CpuFP, NoSuf, { FloatReg } // alias for fxch %st(1) -fxch, 0xd9c9, None, CpuFP, NoSuf, {} +fxch, 0xd9c9, CpuFP, NoSuf, {} // comparison (without pop) -fcom, 0xd8d0, None, CpuFP, NoSuf, { FloatReg } +fcom, 0xd8d0, CpuFP, NoSuf, { FloatReg } // alias for fcom %st(1) -fcom, 0xd8d1, None, CpuFP, NoSuf, {} -fcom, 0xd8, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fcom, 0xd8d0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -ficom, 0xde, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fcom, 0xd8d1, CpuFP, NoSuf, {} +fcom, 0xd8/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fcom, 0xd8d0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +ficom, 0xde/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } // comparison (with pop) -fcomp, 0xd8d8, None, CpuFP, NoSuf, { FloatReg } +fcomp, 0xd8d8, CpuFP, NoSuf, { FloatReg } // alias for fcomp %st(1) -fcomp, 0xd8d9, None, CpuFP, NoSuf, {} -fcomp, 0xd8, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fcomp, 0xd8d8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -ficomp, 0xde, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fcompp, 0xded9, None, CpuFP, NoSuf, {} +fcomp, 0xd8d9, CpuFP, NoSuf, {} +fcomp, 0xd8/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fcomp, 0xd8d8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +ficomp, 0xde/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fcompp, 0xded9, CpuFP, NoSuf, {} // unordered comparison (with pop) -fucom, 0xdde0, None, Cpu387, NoSuf, { FloatReg } +fucom, 0xdde0, Cpu387, NoSuf, { FloatReg } // alias for fucom %st(1) -fucom, 0xdde1, None, Cpu387, NoSuf, {} -fucomp, 0xdde8, None, Cpu387, NoSuf, { FloatReg } +fucom, 0xdde1, Cpu387, NoSuf, {} +fucomp, 0xdde8, Cpu387, NoSuf, { FloatReg } // alias for fucomp %st(1) -fucomp, 0xdde9, None, Cpu387, NoSuf, {} -fucompp, 0xdae9, None, Cpu387, NoSuf, {} +fucomp, 0xdde9, Cpu387, NoSuf, {} +fucompp, 0xdae9, Cpu387, NoSuf, {} -ftst, 0xd9e4, None, CpuFP, NoSuf, {} -fxam, 0xd9e5, None, CpuFP, NoSuf, {} +ftst, 0xd9e4, CpuFP, NoSuf, {} +fxam, 0xd9e5, CpuFP, NoSuf, {} // load constants into %st0 -fld1, 0xd9e8, None, CpuFP, NoSuf, {} -fldl2t, 0xd9e9, None, CpuFP, NoSuf, {} -fldl2e, 0xd9ea, None, CpuFP, NoSuf, {} -fldpi, 0xd9eb, None, CpuFP, NoSuf, {} -fldlg2, 0xd9ec, None, CpuFP, NoSuf, {} -fldln2, 0xd9ed, None, CpuFP, NoSuf, {} -fldz, 0xd9ee, None, CpuFP, NoSuf, {} +fld1, 0xd9e8, CpuFP, NoSuf, {} +fldl2t, 0xd9e9, CpuFP, NoSuf, {} +fldl2e, 0xd9ea, CpuFP, NoSuf, {} +fldpi, 0xd9eb, CpuFP, NoSuf, {} +fldlg2, 0xd9ec, CpuFP, NoSuf, {} +fldln2, 0xd9ed, CpuFP, NoSuf, {} +fldz, 0xd9ee, CpuFP, NoSuf, {} // Arithmetic. // add -fadd, 0xd8c0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fadd, 0xd8c0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fadd %st(i), %st -fadd, 0xd8c0, None, CpuFP, NoSuf, { FloatReg } +fadd, 0xd8c0, CpuFP, NoSuf, { FloatReg } // alias for faddp -fadd, 0xdec1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fadd, 0xd8, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fiadd, 0xde, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fadd, 0xdec1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fadd, 0xd8/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fiadd, 0xde/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -faddp, 0xdec0, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } -faddp, 0xdec0, None, CpuFP, NoSuf, { FloatReg } +faddp, 0xdec0, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } +faddp, 0xdec0, CpuFP, NoSuf, { FloatReg } // alias for faddp %st, %st(1) -faddp, 0xdec1, None, CpuFP, NoSuf, {} +faddp, 0xdec1, CpuFP, NoSuf, {} // subtract -fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } -fsub, 0xd8e0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fsub, 0xd8e0, CpuFP, NoSuf, { FloatReg } +fsub, 0xd8e0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubp -fsub, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fsub, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsub, 0xd8, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fisub, 0xde, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fsubp, 0xdee1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } -fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatReg } -fsubp, 0xdee9, None, CpuFP, NoSuf, {} +fsub, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fsub, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fsub, 0xd8/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fisub, 0xde/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubp, 0xdee1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} +fsubp, 0xdee8, CpuFP, NoSuf, { FloatAcc, FloatReg } +fsubp, 0xdee8, CpuFP, NoSuf, { FloatReg } +fsubp, 0xdee9, CpuFP, NoSuf, {} // subtract reverse -fsubr, 0xd8e8, None, CpuFP, NoSuf, { FloatReg } -fsubr, 0xd8e8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fsubr, 0xd8e8, CpuFP, NoSuf, { FloatReg } +fsubr, 0xd8e8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubrp -fsubr, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fsubr, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsubr, 0xd8, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fisubr, 0xde, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fsubrp, 0xdee9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } -fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatReg } -fsubrp, 0xdee1, None, CpuFP, NoSuf, {} +fsubr, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fsubr, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fsubr, 0xd8/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fisubr, 0xde/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubrp, 0xdee9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} +fsubrp, 0xdee0, CpuFP, NoSuf, { FloatAcc, FloatReg } +fsubrp, 0xdee0, CpuFP, NoSuf, { FloatReg } +fsubrp, 0xdee1, CpuFP, NoSuf, {} // multiply -fmul, 0xd8c8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } -fmul, 0xd8c8, None, CpuFP, NoSuf, { FloatReg } +fmul, 0xd8c8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fmul, 0xd8c8, CpuFP, NoSuf, { FloatReg } // alias for fmulp -fmul, 0xdec9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fmul, 0xd8, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fimul, 0xde, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fmul, 0xdec9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fmul, 0xd8/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fimul, 0xde/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fmulp, 0xdec8, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } -fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatReg } +fmulp, 0xdec8, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } +fmulp, 0xdec8, CpuFP, NoSuf, { FloatReg } // alias for fmulp %st, %st(1) -fmulp, 0xdec9, None, CpuFP, NoSuf, {} +fmulp, 0xdec9, CpuFP, NoSuf, {} // divide -fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } -fdiv, 0xd8f0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fdiv, 0xd8f0, CpuFP, NoSuf, { FloatReg } +fdiv, 0xd8f0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivp -fdiv, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fdiv, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdiv, 0xd8, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fidiv, 0xde, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fdivp, 0xdef1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } -fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatReg } -fdivp, 0xdef9, None, CpuFP, NoSuf, {} +fdiv, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fdiv, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fdiv, 0xd8/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fidiv, 0xde/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivp, 0xdef1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} +fdivp, 0xdef8, CpuFP, NoSuf, { FloatAcc, FloatReg } +fdivp, 0xdef8, CpuFP, NoSuf, { FloatReg } +fdivp, 0xdef9, CpuFP, NoSuf, {} // divide reverse -fdivr, 0xd8f8, None, CpuFP, NoSuf, { FloatReg } -fdivr, 0xd8f8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fdivr, 0xd8f8, CpuFP, NoSuf, { FloatReg } +fdivr, 0xd8f8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivrp -fdivr, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fdivr, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdivr, 0xd8, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fidivr, 0xde, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fdivrp, 0xdef9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } -fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatReg } -fdivrp, 0xdef1, None, CpuFP, NoSuf, {} - -f2xm1, 0xd9f0, None, CpuFP, NoSuf, {} -fyl2x, 0xd9f1, None, CpuFP, NoSuf, {} -fptan, 0xd9f2, None, CpuFP, NoSuf, {} -fpatan, 0xd9f3, None, CpuFP, NoSuf, {} -fxtract, 0xd9f4, None, CpuFP, NoSuf, {} -fprem1, 0xd9f5, None, Cpu387, NoSuf, {} -fdecstp, 0xd9f6, None, CpuFP, NoSuf, {} -fincstp, 0xd9f7, None, CpuFP, NoSuf, {} -fprem, 0xd9f8, None, CpuFP, NoSuf, {} -fyl2xp1, 0xd9f9, None, CpuFP, NoSuf, {} -fsqrt, 0xd9fa, None, CpuFP, NoSuf, {} -fsincos, 0xd9fb, None, Cpu387, NoSuf, {} -frndint, 0xd9fc, None, CpuFP, NoSuf, {} -fscale, 0xd9fd, None, CpuFP, NoSuf, {} -fsin, 0xd9fe, None, Cpu387, NoSuf, {} -fcos, 0xd9ff, None, Cpu387, NoSuf, {} -fchs, 0xd9e0, None, CpuFP, NoSuf, {} -fabs, 0xd9e1, None, CpuFP, NoSuf, {} +fdivr, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fdivr, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} +fdivr, 0xd8/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fidivr, 0xde/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivrp, 0xdef9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} +fdivrp, 0xdef0, CpuFP, NoSuf, { FloatAcc, FloatReg } +fdivrp, 0xdef0, CpuFP, NoSuf, { FloatReg } +fdivrp, 0xdef1, CpuFP, NoSuf, {} + +f2xm1, 0xd9f0, CpuFP, NoSuf, {} +fyl2x, 0xd9f1, CpuFP, NoSuf, {} +fptan, 0xd9f2, CpuFP, NoSuf, {} +fpatan, 0xd9f3, CpuFP, NoSuf, {} +fxtract, 0xd9f4, CpuFP, NoSuf, {} +fprem1, 0xd9f5, Cpu387, NoSuf, {} +fdecstp, 0xd9f6, CpuFP, NoSuf, {} +fincstp, 0xd9f7, CpuFP, NoSuf, {} +fprem, 0xd9f8, CpuFP, NoSuf, {} +fyl2xp1, 0xd9f9, CpuFP, NoSuf, {} +fsqrt, 0xd9fa, CpuFP, NoSuf, {} +fsincos, 0xd9fb, Cpu387, NoSuf, {} +frndint, 0xd9fc, CpuFP, NoSuf, {} +fscale, 0xd9fd, CpuFP, NoSuf, {} +fsin, 0xd9fe, Cpu387, NoSuf, {} +fcos, 0xd9ff, Cpu387, NoSuf, {} +fchs, 0xd9e0, CpuFP, NoSuf, {} +fabs, 0xd9e1, CpuFP, NoSuf, {} // processor control -fninit, 0xdbe3, None, CpuFP, NoSuf, {} -finit, 0xdbe3, None, CpuFP, NoSuf|FWait, {} -fldcw, 0xd9, 5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fnstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } -fnstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word } -fnstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fnstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf, {} -fstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word } -fstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } -fstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf|FWait, {} -fnclex, 0xdbe2, None, CpuFP, NoSuf, {} -fclex, 0xdbe2, None, CpuFP, NoSuf|FWait, {} +fninit, 0xdbe3, CpuFP, NoSuf, {} +finit, 0xdbe3, CpuFP, NoSuf|FWait, {} +fldcw, 0xd9/5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fnstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } +fnstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word } +fnstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fnstsw, 0xdfe0, Cpu287|Cpu387, NoSuf, {} +fstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word } +fstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } +fstsw, 0xdfe0, Cpu287|Cpu387, NoSuf|FWait, {} +fnclex, 0xdbe2, CpuFP, NoSuf, {} +fclex, 0xdbe2, CpuFP, NoSuf|FWait, {} // Short forms of fldenv, fstenv, fsave, and frstor use data size prefix. -fnstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } -fldenv, 0xd9, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fnsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } -frstor, 0xdd, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fnstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } +fldenv, 0xd9/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fnsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } +frstor, 0xdd/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } // 8087 only -fneni, 0xdbe0, None, Cpu8087, NoSuf, {} -feni, 0xdbe0, None, Cpu8087, NoSuf|FWait, {} -fndisi, 0xdbe1, None, Cpu8087, NoSuf, {} -fdisi, 0xdbe1, None, Cpu8087, NoSuf|FWait, {} +fneni, 0xdbe0, Cpu8087, NoSuf, {} +feni, 0xdbe0, Cpu8087, NoSuf|FWait, {} +fndisi, 0xdbe1, Cpu8087, NoSuf, {} +fdisi, 0xdbe1, Cpu8087, NoSuf|FWait, {} // 287 only -fnsetpm, 0xdbe4, None, Cpu287, NoSuf, {} -fsetpm, 0xdbe4, None, Cpu287, NoSuf|FWait, {} -frstpm, 0xdbe5, None, Cpu287, NoSuf, {} +fnsetpm, 0xdbe4, Cpu287, NoSuf, {} +fsetpm, 0xdbe4, Cpu287, NoSuf|FWait, {} +frstpm, 0xdbe5, Cpu287, NoSuf, {} -ffree, 0xddc0, None, CpuFP, NoSuf, { FloatReg } +ffree, 0xddc0, CpuFP, NoSuf, { FloatReg } // P6:free st(i), pop st -ffreep, 0xdfc0, None, Cpu687, NoSuf, { FloatReg } -fnop, 0xd9d0, None, CpuFP, NoSuf, {} -fwait, 0x9b, None, CpuFP, NoSuf, {} +ffreep, 0xdfc0, Cpu687, NoSuf, { FloatReg } +fnop, 0xd9d0, CpuFP, NoSuf, {} +fwait, 0x9b, CpuFP, NoSuf, {} // Opcode prefixes; we allow them as separate insns too. -addr16, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} -addr32, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} -aword, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} -adword, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} -data16, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} -data32, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} -word, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} -dword, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} -lock, 0xf0, None, 0, NoSuf|IsPrefix, {} -wait, 0x9b, None, 0, NoSuf|IsPrefix, {} -cs, 0x2e, None, 0, NoSuf|IsPrefix, {} -ds, 0x3e, None, 0, NoSuf|IsPrefix, {} -es, 0x26, None, CpuNo64, NoSuf|IsPrefix, {} -fs, 0x64, None, Cpu386, NoSuf|IsPrefix, {} -gs, 0x65, None, Cpu386, NoSuf|IsPrefix, {} -ss, 0x36, None, CpuNo64, NoSuf|IsPrefix, {} -rep, 0xf3, None, 0, NoSuf|IsPrefix, {} -repe, 0xf3, None, 0, NoSuf|IsPrefix, {} -repz, 0xf3, None, 0, NoSuf|IsPrefix, {} -repne, 0xf2, None, 0, NoSuf|IsPrefix, {} -repnz, 0xf2, None, 0, NoSuf|IsPrefix, {} -ht, 0x3e, None, 0, NoSuf|IsPrefix, {} -hnt, 0x2e, None, 0, NoSuf|IsPrefix, {} -rex, 0x40, None, Cpu64, NoSuf|IsPrefix, {} -rexz, 0x41, None, Cpu64, NoSuf|IsPrefix, {} -rexy, 0x42, None, Cpu64, NoSuf|IsPrefix, {} -rexyz, 0x43, None, Cpu64, NoSuf|IsPrefix, {} -rexx, 0x44, None, Cpu64, NoSuf|IsPrefix, {} -rexxz, 0x45, None, Cpu64, NoSuf|IsPrefix, {} -rexxy, 0x46, None, Cpu64, NoSuf|IsPrefix, {} -rexxyz, 0x47, None, Cpu64, NoSuf|IsPrefix, {} -rex64, 0x48, None, Cpu64, NoSuf|IsPrefix, {} -rex64z, 0x49, None, Cpu64, NoSuf|IsPrefix, {} -rex64y, 0x4a, None, Cpu64, NoSuf|IsPrefix, {} -rex64yz, 0x4b, None, Cpu64, NoSuf|IsPrefix, {} -rex64x, 0x4c, None, Cpu64, NoSuf|IsPrefix, {} -rex64xz, 0x4d, None, Cpu64, NoSuf|IsPrefix, {} -rex64xy, 0x4e, None, Cpu64, NoSuf|IsPrefix, {} -rex64xyz, 0x4f, None, Cpu64, NoSuf|IsPrefix, {} -rex.b, 0x41, None, Cpu64, NoSuf|IsPrefix, {} -rex.x, 0x42, None, Cpu64, NoSuf|IsPrefix, {} -rex.xb, 0x43, None, Cpu64, NoSuf|IsPrefix, {} -rex.r, 0x44, None, Cpu64, NoSuf|IsPrefix, {} -rex.rb, 0x45, None, Cpu64, NoSuf|IsPrefix, {} -rex.rx, 0x46, None, Cpu64, NoSuf|IsPrefix, {} -rex.rxb, 0x47, None, Cpu64, NoSuf|IsPrefix, {} -rex.w, 0x48, None, Cpu64, NoSuf|IsPrefix, {} -rex.wb, 0x49, None, Cpu64, NoSuf|IsPrefix, {} -rex.wx, 0x4a, None, Cpu64, NoSuf|IsPrefix, {} -rex.wxb, 0x4b, None, Cpu64, NoSuf|IsPrefix, {} -rex.wr, 0x4c, None, Cpu64, NoSuf|IsPrefix, {} -rex.wrb, 0x4d, None, Cpu64, NoSuf|IsPrefix, {} -rex.wrx, 0x4e, None, Cpu64, NoSuf|IsPrefix, {} -rex.wrxb, 0x4f, None, Cpu64, NoSuf|IsPrefix, {} +addr16, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} +addr32, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} +aword, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} +adword, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} +data16, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +data32, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} +word, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +dword, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} +lock, 0xf0, 0, NoSuf|IsPrefix, {} +wait, 0x9b, 0, NoSuf|IsPrefix, {} +cs, 0x2e, 0, NoSuf|IsPrefix, {} +ds, 0x3e, 0, NoSuf|IsPrefix, {} +es, 0x26, CpuNo64, NoSuf|IsPrefix, {} +fs, 0x64, Cpu386, NoSuf|IsPrefix, {} +gs, 0x65, Cpu386, NoSuf|IsPrefix, {} +ss, 0x36, CpuNo64, NoSuf|IsPrefix, {} +rep, 0xf3, 0, NoSuf|IsPrefix, {} +repe, 0xf3, 0, NoSuf|IsPrefix, {} +repz, 0xf3, 0, NoSuf|IsPrefix, {} +repne, 0xf2, 0, NoSuf|IsPrefix, {} +repnz, 0xf2, 0, NoSuf|IsPrefix, {} +ht, 0x3e, 0, NoSuf|IsPrefix, {} +hnt, 0x2e, 0, NoSuf|IsPrefix, {} +rex, 0x40, Cpu64, NoSuf|IsPrefix, {} +rexz, 0x41, Cpu64, NoSuf|IsPrefix, {} +rexy, 0x42, Cpu64, NoSuf|IsPrefix, {} +rexyz, 0x43, Cpu64, NoSuf|IsPrefix, {} +rexx, 0x44, Cpu64, NoSuf|IsPrefix, {} +rexxz, 0x45, Cpu64, NoSuf|IsPrefix, {} +rexxy, 0x46, Cpu64, NoSuf|IsPrefix, {} +rexxyz, 0x47, Cpu64, NoSuf|IsPrefix, {} +rex64, 0x48, Cpu64, NoSuf|IsPrefix, {} +rex64z, 0x49, Cpu64, NoSuf|IsPrefix, {} +rex64y, 0x4a, Cpu64, NoSuf|IsPrefix, {} +rex64yz, 0x4b, Cpu64, NoSuf|IsPrefix, {} +rex64x, 0x4c, Cpu64, NoSuf|IsPrefix, {} +rex64xz, 0x4d, Cpu64, NoSuf|IsPrefix, {} +rex64xy, 0x4e, Cpu64, NoSuf|IsPrefix, {} +rex64xyz, 0x4f, Cpu64, NoSuf|IsPrefix, {} +rex.b, 0x41, Cpu64, NoSuf|IsPrefix, {} +rex.x, 0x42, Cpu64, NoSuf|IsPrefix, {} +rex.xb, 0x43, Cpu64, NoSuf|IsPrefix, {} +rex.r, 0x44, Cpu64, NoSuf|IsPrefix, {} +rex.rb, 0x45, Cpu64, NoSuf|IsPrefix, {} +rex.rx, 0x46, Cpu64, NoSuf|IsPrefix, {} +rex.rxb, 0x47, Cpu64, NoSuf|IsPrefix, {} +rex.w, 0x48, Cpu64, NoSuf|IsPrefix, {} +rex.wb, 0x49, Cpu64, NoSuf|IsPrefix, {} +rex.wx, 0x4a, Cpu64, NoSuf|IsPrefix, {} +rex.wxb, 0x4b, Cpu64, NoSuf|IsPrefix, {} +rex.wr, 0x4c, Cpu64, NoSuf|IsPrefix, {} +rex.wrb, 0x4d, Cpu64, NoSuf|IsPrefix, {} +rex.wrx, 0x4e, Cpu64, NoSuf|IsPrefix, {} +rex.wrxb, 0x4f, Cpu64, NoSuf|IsPrefix, {} // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) @@ -867,89 +866,89 @@ rex.wrxb, 0x4f, None, Cpu64, NoSuf|IsPrefix, {} vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, + rex:REX:Cpu64, nooptimize:NoOptimize:0> -{}, PSEUDO_PREFIX, Prefix_, , NoSuf|IsPrefix, {} +{}, PSEUDO_PREFIX/Prefix_, , NoSuf|IsPrefix, {} // 486 extensions. -bswap, 0xfc8, None, Cpu486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } -xadd, 0xfc0, None, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -cmpxchg, 0xfb0, None, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -invd, 0xf08, None, Cpu486, NoSuf, {} -wbinvd, 0xf09, None, Cpu486, NoSuf, {} -invlpg, 0xf01, 7, Cpu486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +bswap, 0xfc8, Cpu486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } +xadd, 0xfc0, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +cmpxchg, 0xfb0, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +invd, 0xf08, Cpu486, NoSuf, {} +wbinvd, 0xf09, Cpu486, NoSuf, {} +invlpg, 0xf01/7, Cpu486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // 586 and late 486 extensions. -cpuid, 0xfa2, None, Cpu486, NoSuf, {} +cpuid, 0xfa2, Cpu486, NoSuf, {} // Pentium extensions. -wrmsr, 0xf30, None, Cpu586, NoSuf, {} -rdtsc, 0xf31, None, Cpu586, NoSuf, {} -rdmsr, 0xf32, None, Cpu586, NoSuf, {} -cmpxchg8b, 0xfc7, 1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } +wrmsr, 0xf30, Cpu586, NoSuf, {} +rdtsc, 0xf31, Cpu586, NoSuf, {} +rdmsr, 0xf32, Cpu586, NoSuf, {} +cmpxchg8b, 0xfc7/1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } // Pentium II/Pentium Pro extensions. -sysenter, 0xf34, None, Cpu64, Intel64Only|NoSuf, {} -sysenter, 0xf34, None, Cpu686|CpuNo64, NoSuf, {} -sysexit, 0xf35, None, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} -sysexit, 0xf35, None, Cpu686|CpuNo64, NoSuf, {} -fxsave, 0xfae, 0, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -fxsave64, 0xfae, 0, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -fxrstor, 0xfae, 1, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -fxrstor64, 0xfae, 1, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -rdpmc, 0xf33, None, Cpu686, NoSuf, {} +sysenter, 0xf34, Cpu64, Intel64Only|NoSuf, {} +sysenter, 0xf34, Cpu686|CpuNo64, NoSuf, {} +sysexit, 0xf35, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} +sysexit, 0xf35, Cpu686|CpuNo64, NoSuf, {} +fxsave, 0xfae/0, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +fxsave64, 0xfae/0, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +fxrstor, 0xfae/1, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +fxrstor64, 0xfae/1, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +rdpmc, 0xf33, Cpu686, NoSuf, {} // official undefined instr. -ud2, 0xf0b, None, Cpu186, NoSuf, {} +ud2, 0xf0b, Cpu186, NoSuf, {} // alias for ud2 -ud2a, 0xf0b, None, Cpu186, NoSuf, {} +ud2a, 0xf0b, Cpu186, NoSuf, {} // 2nd. official undefined instr. -ud1, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud1, 0xfb9, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // alias for ud1 -ud2b, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud2b, 0xfb9, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // 3rd official undefined instr (older CPUs don't take a ModR/M byte) -ud0, 0xfff, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } - -cmov, 0xf4, None, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } - -fcmovb, 0xdac0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnae, 0xdac0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmove, 0xdac8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovbe, 0xdad0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovna, 0xdad0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovu, 0xdad8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovae, 0xdbc0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnb, 0xdbc0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovne, 0xdbc8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmova, 0xdbd0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnbe, 0xdbd0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnu, 0xdbd8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } - -fcomi, 0xdbf0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcomi, 0xdbf1, None, Cpu687, NoSuf, {} -fcomi, 0xdbf0, None, Cpu687, NoSuf, { FloatReg } -fucomi, 0xdbe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucomi, 0xdbe9, None, Cpu687, NoSuf, {} -fucomi, 0xdbe8, None, Cpu687, NoSuf, { FloatReg } -fcomip, 0xdff0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcomip, 0xdff1, None, Cpu687, NoSuf, {} -fcomip, 0xdff0, None, Cpu687, NoSuf, { FloatReg } -fcompi, 0xdff0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcompi, 0xdff1, None, Cpu687, NoSuf, {} -fcompi, 0xdff0, None, Cpu687, NoSuf, { FloatReg } -fucomip, 0xdfe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucomip, 0xdfe9, None, Cpu687, NoSuf, {} -fucomip, 0xdfe8, None, Cpu687, NoSuf, { FloatReg } -fucompi, 0xdfe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucompi, 0xdfe9, None, Cpu687, NoSuf, {} -fucompi, 0xdfe8, None, Cpu687, NoSuf, { FloatReg } +ud0, 0xfff, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +cmov, 0xf4, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +fcmovb, 0xdac0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovnae, 0xdac0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmove, 0xdac8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovbe, 0xdad0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovna, 0xdad0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovu, 0xdad8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovae, 0xdbc0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovnb, 0xdbc0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovne, 0xdbc8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmova, 0xdbd0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovnbe, 0xdbd0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcmovnu, 0xdbd8, Cpu687, NoSuf, { FloatReg, FloatAcc } + +fcomi, 0xdbf0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcomi, 0xdbf1, Cpu687, NoSuf, {} +fcomi, 0xdbf0, Cpu687, NoSuf, { FloatReg } +fucomi, 0xdbe8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fucomi, 0xdbe9, Cpu687, NoSuf, {} +fucomi, 0xdbe8, Cpu687, NoSuf, { FloatReg } +fcomip, 0xdff0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcomip, 0xdff1, Cpu687, NoSuf, {} +fcomip, 0xdff0, Cpu687, NoSuf, { FloatReg } +fcompi, 0xdff0, Cpu687, NoSuf, { FloatReg, FloatAcc } +fcompi, 0xdff1, Cpu687, NoSuf, {} +fcompi, 0xdff0, Cpu687, NoSuf, { FloatReg } +fucomip, 0xdfe8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fucomip, 0xdfe9, Cpu687, NoSuf, {} +fucomip, 0xdfe8, Cpu687, NoSuf, { FloatReg } +fucompi, 0xdfe8, Cpu687, NoSuf, { FloatReg, FloatAcc } +fucompi, 0xdfe9, Cpu687, NoSuf, {} +fucompi, 0xdfe8, Cpu687, NoSuf, { FloatReg } // Pentium4 extensions. -movnti, 0xfc3, None, CpuSSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -clflush, 0xfae, 7, CpuClflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -lfence, 0xfaee8, None, CpuSSE2, NoSuf, {} -mfence, 0xfaef0, None, CpuSSE2, NoSuf, {} +movnti, 0xfc3, CpuSSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +clflush, 0xfae/7, CpuClflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +lfence, 0xfaee8, CpuSSE2, NoSuf, {} +mfence, 0xfaef0, CpuSSE2, NoSuf, {} // Processors that do not support PAUSE treat this opcode as a NOP instruction. -pause, 0xf390, None, Cpu186, NoSuf, {} +pause, 0xf390, Cpu186, NoSuf, {} // MMX/SSE2 instructions. @@ -970,74 +969,74 @@ pause, 0xf390, None, Cpu186, NoSuf, {} d:0:VexW0::Dword::Reg32:66, + q:1:VexW1:VexW1:Qword:Cpu64:Reg64:> -emms, 0xf77, None, CpuMMX, NoSuf, {} +emms, 0xf77, CpuMMX, NoSuf, {} // These really shouldn't allow for Reg64 (movq is the right mnemonic for // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's // spec). AMD's spec, having been in existence for much longer, failed to // recognize that and specified movd for 32- and 64-bit operations. -movd, 0x666e, None, CpuAVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } -movd, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } -movd, 0x660f6e, None, CpuSSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -movd, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } +movd, 0x666e, CpuAVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } +movd, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } +movd, 0x660f6e, CpuSSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +movd, 0x660f6e, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } // The MMX templates have to remain after at least the SSE2AVX ones. -movd, 0xf6e, None, CpuMMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } -movd, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } -movq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movq, 0x66d6, None, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -movq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } -movq, 0xf30f7e, None, CpuSSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } -movq, 0x660fd6, None, CpuSSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } -movq, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } +movd, 0xf6e, CpuMMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } +movd, 0xf6e, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } +movq, 0xf37e, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movq, 0x66d6, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +movq, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } +movq, 0xf30f7e, CpuSSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } +movq, 0x660fd6, CpuSSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } +movq, 0x660f6e, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } // The MMX templates have to remain after at least the SSE2AVX ones. -movq, 0xf6f, None, CpuMMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } -movq, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } -packssdw, 0x0f6b, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -packsswb, 0x0f63, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -packuswb, 0x0f67, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -padd, 0x0ffc | , None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -paddd, 0x0ffe, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -paddq, 0x660fd4, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -paddq, 0xfd4, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -padds, 0x0fec | , None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -paddus, 0x0fdc | , None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pand, 0x0fdb, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pandn, 0x0fdf, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -pcmpeq, 0x0f74 | , None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pcmpeqd, 0x0f76, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pcmpgt, 0x0f64 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -pcmpgtd, 0x0f66, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -pmaddwd, 0x0ff5, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pmulhw, 0x0fe5, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -pmullw, 0x0fd5, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -por, 0x0feb, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } -psllw, 0x0ff1, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psllw, 0x0f71, 6, , Modrm||NoSuf, { Imm8, } -psll, 0x0ff2 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psll, 0x0f72 | , 6, , Modrm||NoSuf, { Imm8, } -psraw, 0x0fe1, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psraw, 0x0f71, 4, , Modrm||NoSuf, { Imm8, } -psrad, 0x0fe2, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psrad, 0x0f72, 4, , Modrm||NoSuf, { Imm8, } -psrlw, 0x0fd1, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psrlw, 0x0f71, 2, , Modrm||NoSuf, { Imm8, } -psrl, 0x0fd2 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psrl, 0x0f72 | , 2, , Modrm||NoSuf, { Imm8, } -psub, 0x0ff8 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psubd, 0x0ffa, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psubq, 0x660ffb, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -psubq, 0xffb, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -psubs, 0x0fe8 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -psubus, 0x0fd8 | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -punpckhbw, 0x0f68, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -punpckhwd, 0x0f69, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -punpckhdq, 0x0f6a, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -punpcklbw, 0x660f60, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpcklbw, 0xf60, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } -punpcklwd, 0x660f61, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpcklwd, 0xf61, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } -punpckldq, 0x660f62, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpckldq, 0xf62, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } -pxor, 0x0fef, None, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +movq, 0xf6f, CpuMMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } +movq, 0xf6e, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } +packssdw, 0x0f6b, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +packsswb, 0x0f63, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +packuswb, 0x0f67, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +padd, 0x0ffc | , , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +paddd, 0x0ffe, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +paddq, 0x660fd4, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +paddq, 0xfd4, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +padds, 0x0fec | , , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +paddus, 0x0fdc | , , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pand, 0x0fdb, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pandn, 0x0fdf, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +pcmpeq, 0x0f74 | , , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pcmpeqd, 0x0f76, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pcmpgt, 0x0f64 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +pcmpgtd, 0x0f66, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +pmaddwd, 0x0ff5, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pmulhw, 0x0fe5, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +pmullw, 0x0fd5, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +por, 0x0feb, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } +psllw, 0x0ff1, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psllw, 0x0f71/6, , Modrm||NoSuf, { Imm8, } +psll, 0x0ff2 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psll, 0x0f72 | /6, , Modrm||NoSuf, { Imm8, } +psraw, 0x0fe1, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psraw, 0x0f71/4, , Modrm||NoSuf, { Imm8, } +psrad, 0x0fe2, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psrad, 0x0f72/4, , Modrm||NoSuf, { Imm8, } +psrlw, 0x0fd1, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psrlw, 0x0f71/2, , Modrm||NoSuf, { Imm8, } +psrl, 0x0fd2 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psrl, 0x0f72 | /2, , Modrm||NoSuf, { Imm8, } +psub, 0x0ff8 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psubd, 0x0ffa, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psubq, 0x660ffb, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +psubq, 0xffb, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +psubs, 0x0fe8 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +psubus, 0x0fd8 | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +punpckhbw, 0x0f68, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +punpckhwd, 0x0f69, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +punpckhdq, 0x0f6a, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +punpcklbw, 0x660f60, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +punpcklbw, 0xf60, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +punpcklwd, 0x660f61, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +punpcklwd, 0xf61, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +punpckldq, 0x660f62, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +punpckldq, 0xf62, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +pxor, 0x0fef, , Modrm||C|NoSuf, { ||Unspecified|BaseIndex, } // SSE instructions. @@ -1046,179 +1045,179 @@ pxor, 0x0fef, None, , Modrm||C|NoSuf, { -addps, 0x0f58, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -addss, 0xf30f58, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -andnps, 0x0f55, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -andps, 0x0f54, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cmpps, 0x0fc2, , , Modrm||||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -cmpss, 0xf30fc2, , , Modrm||||NoSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -cmpps, 0x0fc2, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -cmpss, 0xf30fc2, None, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -comiss, 0x0f2f, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtpi2ps, 0xf2a, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } -cvtps2pi, 0xf2d, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } -cvtsi2ss, 0xf30f2a, None, |CpuNo64, Modrm|||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtss2si, 0xf32d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvtss2si, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttps2pi, 0xf2c, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } -cvttss2si, 0xf32c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttss2si, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -divps, 0x0f5e, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -divss, 0xf30f5e, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -ldmxcsr, 0x0fae, 2, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex } -maskmovq, 0xff7, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } -maxps, 0x0f5f, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -maxss, 0xf30f5f, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -minps, 0x0f5d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -minss, 0xf30f5d, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -movaps, 0x0f28, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movhlps, 0x0f12, None, , Modrm|||NoSuf, { RegXMM, RegXMM } -movhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movhps, 0xf16, None, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movlhps, 0x0f16, None, , Modrm|||NoSuf, { RegXMM, RegXMM } -movlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movlps, 0xf12, None, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movmskps, 0x0f50, None, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } -movntps, 0x0f2b, None, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movntq, 0xfe7, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } -movntdq, 0x660fe7, None, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movss, 0xf310, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } -movss, 0xf310, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } -movss, 0xf30f10, None, CpuSSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -movups, 0x0f10, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -mulps, 0x0f59, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -mulss, 0xf30f59, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -orps, 0x0f56, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pavg, 0xfe0 | (3 * ), None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pavg, 0x660fe0 | (3 * ), None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pextrw, 0x660fc5, None, , Load|Modrm||No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } -pextrw, 0xfc5, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } -pinsrw, 0x660fc4, None, , Modrm|||No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } -pinsrw, 0x660fc4, None, , Modrm|||NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM } -pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } -pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } -pmaxsw, 0x660fee, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxsw, 0xfee, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pmaxub, 0x660fde, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxub, 0xfde, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pminsw, 0x660fea, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminsw, 0xfea, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pminub, 0x660fda, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminub, 0xfda, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pmovmskb, 0x660fd7, None, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } -pmovmskb, 0xfd7, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegMMX, Reg32|Reg64 } -pmulhuw, 0x660fe4, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmulhuw, 0xfe4, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -prefetchnta, 0xf18, 0, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht0, 0xf18, 1, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht1, 0xf18, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht2, 0xf18, 3, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -psadbw, 0xff6, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -psadbw, 0x660ff6, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pshufw, 0xf70, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -rcpps, 0x0f53, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -rcpss, 0xf30f53, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -rsqrtps, 0x0f52, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -rsqrtss, 0xf30f52, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -sfence, 0xfaef8, None, CpuSSE|Cpu3dnowA, NoSuf, {} -shufps, 0x0fc6, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -sqrtps, 0x0f51, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sqrtss, 0xf30f51, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -stmxcsr, 0x0fae, 3, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex } -subps, 0x0f5c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -subss, 0xf30f5c, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -ucomiss, 0x0f2e, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -unpckhps, 0x0f15, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -unpcklps, 0x0f14, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -xorps, 0x0f57, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addps, 0x0f58, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addss, 0xf30f58, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +andnps, 0x0f55, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +andps, 0x0f54, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cmpps, 0x0fc2/, , Modrm||||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +cmpss, 0xf30fc2/, , Modrm||||NoSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +cmpps, 0x0fc2, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +cmpss, 0xf30fc2, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +comiss, 0x0f2f, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +cvtpi2ps, 0xf2a, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } +cvtps2pi, 0xf2d, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +cvtsi2ss, 0xf30f2a, |CpuNo64, Modrm|||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf32a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf32a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf30f2a, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf30f2a, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtss2si, 0xf32d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtss2si, 0xf30f2d, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttps2pi, 0xf2c, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +cvttss2si, 0xf32c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttss2si, 0xf30f2c, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +divps, 0x0f5e, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +divss, 0xf30f5e, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +ldmxcsr, 0x0fae/2, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex } +maskmovq, 0xff7, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } +maxps, 0x0f5f, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +maxss, 0xf30f5f, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +minps, 0x0f5d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +minss, 0xf30f5d, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +movaps, 0x0f28, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +movhlps, 0x0f12, , Modrm|||NoSuf, { RegXMM, RegXMM } +movhps, 0x16, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movhps, 0x17, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movhps, 0xf16, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movlhps, 0x0f16, , Modrm|||NoSuf, { RegXMM, RegXMM } +movlps, 0x12, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movlps, 0x13, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movlps, 0xf12, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movmskps, 0x0f50, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntps, 0x0f2b, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } +movntq, 0xfe7, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } +movntdq, 0x660fe7, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } +movss, 0xf310, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } +movss, 0xf310, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movss, 0xf30f10, CpuSSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +movups, 0x0f10, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +mulps, 0x0f59, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +mulss, 0xf30f59, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +orps, 0x0f56, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pavg, 0xfe0 | (3 * ), CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pavg, 0x660fe0 | (3 * ), , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pextrw, 0x660fc5, , Load|Modrm||No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 0xfc5, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } +pinsrw, 0x660fc4, , Modrm|||No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } +pinsrw, 0x660fc4, , Modrm|||NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM } +pinsrw, 0xfc4, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } +pinsrw, 0xfc4, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } +pmaxsw, 0x660fee, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmaxsw, 0xfee, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmaxub, 0x660fde, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmaxub, 0xfde, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pminsw, 0x660fea, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminsw, 0xfea, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pminub, 0x660fda, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminub, 0xfda, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmovmskb, 0x660fd7, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } +pmovmskb, 0xfd7, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegMMX, Reg32|Reg64 } +pmulhuw, 0x660fe4, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmulhuw, 0xfe4, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +prefetchnta, 0xf18/0, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht0, 0xf18/1, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht1, 0xf18/2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht2, 0xf18/3, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +psadbw, 0xff6, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +psadbw, 0x660ff6, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pshufw, 0xf70, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +rcpps, 0x0f53, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +rcpss, 0xf30f53, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +rsqrtps, 0x0f52, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +rsqrtss, 0xf30f52, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +sfence, 0xfaef8, CpuSSE|Cpu3dnowA, NoSuf, {} +shufps, 0x0fc6, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +sqrtps, 0x0f51, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sqrtss, 0xf30f51, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +stmxcsr, 0x0fae/3, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex } +subps, 0x0f5c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +subss, 0xf30f5c, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +ucomiss, 0x0f2e, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +unpckhps, 0x0f15, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +unpcklps, 0x0f14, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +xorps, 0x0f57, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // SSE2 instructions. -addpd, 0x660f58, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -addsd, 0xf20f58, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -andnpd, 0x660f55, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -andpd, 0x660f54, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cmppd, 0x660fc2, , , Modrm||||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -cmpsd, 0xf20fc2, , , Modrm||||NoSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -cmppd, 0x660fc2, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -cmpsd, 0xf20fc2, None, , Modrm|||NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -comisd, 0x660f2f, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } -cvtpi2pd, 0xf3e6, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf20f2a, None, |CpuNo64, Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf20f2a, None, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf20f2a, None, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -divpd, 0x660f5e, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -divsd, 0xf20f5e, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -maxpd, 0x660f5f, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -maxsd, 0xf20f5f, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -minpd, 0x660f5d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -minsd, 0xf20f5d, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movapd, 0x660f28, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movhpd, 0x660f16, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movlpd, 0x660f12, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movmskpd, 0x660f50, None, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } -movntpd, 0x660f2b, None, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movsd, 0xf210, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } -movsd, 0xf20f10, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movupd, 0x660f10, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -mulpd, 0x660f59, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -mulsd, 0xf20f59, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -orpd, 0x660f56, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -shufpd, 0x660fc6, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -sqrtpd, 0x660f51, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sqrtsd, 0xf20f51, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -subpd, 0x660f5c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -subsd, 0xf20f5c, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -ucomisd, 0x660f2e, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -unpckhpd, 0x660f15, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -unpcklpd, 0x660f14, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -xorpd, 0x660f57, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtdq2pd, 0xf30fe6, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtpd2dq, 0xf20fe6, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtdq2ps, 0x0f5b, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtpd2pi, 0x660f2d, None, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } -cvtpd2ps, 0x660f5a, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtps2pd, 0x0f5a, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtps2dq, 0x660f5b, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtsd2si, 0xf22d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvtsd2si, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvtsd2ss, 0xf20f5a, None, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtss2sd, 0xf30f5a, None, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } - -cvttpd2pi, 0x660f2c, None, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } -cvttsd2si, 0xf22c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttsd2si, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttpd2dq, 0x660fe6, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvttps2dq, 0xf30f5b, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -maskmovdqu, 0x660ff7, None, , Modrm||NoSuf, { RegXMM, RegXMM } -movdqa, 0x660f6f, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movdqu, 0xf30f6f, None, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movdq2q, 0xf20fd6, None, CpuSSE2, Modrm|NoSuf, { RegXMM, RegMMX } -movq2dq, 0xf30fd6, None, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } -pmuludq, 0x660ff4, None, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmuludq, 0xff4, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pshufd, 0x660f70, None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pshufhw, 0xf30f70, None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pshuflw, 0xf20f70, None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pslldq, 0x660f73, 7, , Modrm||NoSuf, { Imm8, RegXMM } -psrldq, 0x660f73, 3, , Modrm||NoSuf, { Imm8, RegXMM } -punpckhqdq, 0x660f6d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpcklqdq, 0x660f6c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addpd, 0x660f58, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addsd, 0xf20f58, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +andnpd, 0x660f55, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +andpd, 0x660f54, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cmppd, 0x660fc2/, , Modrm||||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +cmpsd, 0xf20fc2/, , Modrm||||NoSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +cmppd, 0x660fc2, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +cmpsd, 0xf20fc2, , Modrm|||NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +comisd, 0x660f2f, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +cvtpi2pd, 0x660f2a, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } +cvtpi2pd, 0xf3e6, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +cvtpi2pd, 0x660f2a, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf20f2a, |CpuNo64, Modrm|IgnoreSize|||No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf22a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf22a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf20f2a, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf20f2a, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +divpd, 0x660f5e, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +divsd, 0xf20f5e, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +maxpd, 0x660f5f, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +maxsd, 0xf20f5f, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +minpd, 0x660f5d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +minsd, 0xf20f5d, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movapd, 0x660f28, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +movhpd, 0x6616, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movhpd, 0x6617, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movhpd, 0x660f16, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movlpd, 0x6612, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movlpd, 0x6613, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movlpd, 0x660f12, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movmskpd, 0x660f50, , Modrm||IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntpd, 0x660f2b, , Modrm||NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } +movsd, 0xf210, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movsd, 0xf210, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movsd, 0xf20f10, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movupd, 0x660f10, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +mulpd, 0x660f59, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +mulsd, 0xf20f59, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +orpd, 0x660f56, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +shufpd, 0x660fc6, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +sqrtpd, 0x660f51, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sqrtsd, 0xf20f51, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +subpd, 0x660f5c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +subsd, 0xf20f5c, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +ucomisd, 0x660f2e, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +unpckhpd, 0x660f15, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +unpcklpd, 0x660f14, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +xorpd, 0x660f57, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvtdq2pd, 0xf30fe6, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +cvtpd2dq, 0xf20fe6, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvtdq2ps, 0x0f5b, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvtpd2pi, 0x660f2d, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } +cvtpd2ps, 0x660f5a, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvtps2pd, 0x0f5a, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +cvtps2dq, 0x660f5b, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvtsd2si, 0xf22d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtsd2si, 0xf20f2d, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtsd2ss, 0xf20f5a, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +cvtss2sd, 0xf30f5a, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } + +cvttpd2pi, 0x660f2c, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } +cvttsd2si, 0xf22c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttsd2si, 0xf20f2c, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttpd2dq, 0x660fe6, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +cvttps2dq, 0xf30f5b, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +maskmovdqu, 0x660ff7, , Modrm||NoSuf, { RegXMM, RegXMM } +movdqa, 0x660f6f, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +movdqu, 0xf30f6f, , D|Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +movdq2q, 0xf20fd6, CpuSSE2, Modrm|NoSuf, { RegXMM, RegMMX } +movq2dq, 0xf30fd6, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } +pmuludq, 0x660ff4, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmuludq, 0xff4, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pshufd, 0x660f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pshufhw, 0xf30f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pshuflw, 0xf20f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pslldq, 0x660f73/7, , Modrm||NoSuf, { Imm8, RegXMM } +psrldq, 0x660f73/3, , Modrm||NoSuf, { Imm8, RegXMM } +punpckhqdq, 0x660f6d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +punpcklqdq, 0x660f6c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1226,75 +1225,75 @@ punpcklqdq, 0x660f6c, None, , Modrm|||NoSu -addsubpd, 0x660fd0, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -addsubps, 0xf20fd0, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -haddpd, 0x660f7c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -haddps, 0xf20f7c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -hsubpd, 0x660f7d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -hsubps, 0xf20f7d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -lddqu, 0xf20ff0, None, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } -movddup, 0xf20f12, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movshdup, 0xf30f16, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movsldup, 0xf30f12, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addsubpd, 0x660fd0, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +addsubps, 0xf20fd0, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +haddpd, 0x660f7c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +haddps, 0xf20f7c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +hsubpd, 0x660f7d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +hsubps, 0xf20f7d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +lddqu, 0xf20ff0, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } +movddup, 0xf20f12, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movshdup, 0xf30f16, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +movsldup, 0xf30f12, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // FPU instructions also covered by SSE3 CPUID flag. -fisttp, 0xdf, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fisttp, 0xdd, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fisttpll, 0xdd, 1, CpuFISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fisttp, 0xdf/1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fisttp, 0xdd/1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fisttpll, 0xdd/1, CpuFISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } // CMPXCHG16B instruction. -cmpxchg16b, 0xfc7, 1, CpuCX16|Cpu64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } +cmpxchg16b, 0xfc7/1, CpuCX16|Cpu64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } // MONITOR instructions. -monitor, 0xf01c8, None, CpuSSE3, NoSuf, {} +monitor, 0xf01c8, CpuSSE3, NoSuf, {} // monitor is very special. CX and DX are always 32 bits. The // address size override prefix can be used to overrride the AX size in // all modes. -monitor, 0xf01c8, None, CpuSSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +monitor, 0xf01c8, CpuSSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // The 64-bit form exists only for compatibility with older gas. -monitor, 0xf01c8, None, CpuSSE3|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } -mwait, 0xf01c9, None, CpuSSE3, NoSuf, {} +monitor, 0xf01c8, CpuSSE3|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +mwait, 0xf01c9, CpuSSE3, NoSuf, {} // mwait is very special. AX and CX are always 32 bits. // The 64-bit form exists only for compatibility with older gas. -mwait, 0xf01c9, None, CpuSSE3, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } +mwait, 0xf01c9, CpuSSE3, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } // VMX instructions. -vmcall, 0xf01c1, None, CpuVMX, NoSuf, {} -vmclear, 0x660fc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmlaunch, 0xf01c2, None, CpuVMX, NoSuf, {} -vmresume, 0xf01c3, None, CpuVMX, NoSuf, {} -vmptrld, 0xfc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmptrst, 0xfc7, 7, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmread, 0xf78, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } -vmread, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } -vmwrite, 0xf79, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } -vmwrite, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } -vmxoff, 0xf01c4, None, CpuVMX, NoSuf, {} -vmxon, 0xf30fc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmcall, 0xf01c1, CpuVMX, NoSuf, {} +vmclear, 0x660fc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmlaunch, 0xf01c2, CpuVMX, NoSuf, {} +vmresume, 0xf01c3, CpuVMX, NoSuf, {} +vmptrld, 0xfc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmptrst, 0xfc7/7, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmread, 0xf78, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } +vmread, 0xf78, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } +vmwrite, 0xf79, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } +vmwrite, 0xf79, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } +vmxoff, 0xf01c4, CpuVMX, NoSuf, {} +vmxon, 0xf30fc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } // VMFUNC instruction -vmfunc, 0xf01d4, None, CpuVMFUNC, NoSuf, {} +vmfunc, 0xf01d4, CpuVMFUNC, NoSuf, {} // SMX instructions. -getsec, 0xf37, None, CpuSMX, NoSuf, {} +getsec, 0xf37, CpuSMX, NoSuf, {} // EPT instructions. -invept, 0x660f3880, None, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invept, 0x660f3880, None, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } -invvpid, 0x660f3881, None, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invvpid, 0x660f3881, None, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invept, 0x660f3880, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invept, 0x660f3880, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invvpid, 0x660f3881, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invvpid, 0x660f3881, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } // INVPCID instruction -invpcid, 0x660f3882, None, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invpcid, 0x660f3882, None, CpuINVPCID|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invpcid, 0x660f3882, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invpcid, 0x660f3882, CpuINVPCID|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } // SSSE3 instructions. @@ -1303,147 +1302,147 @@ invpcid, 0x660f3882, None, CpuINVPCID|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspec $sse:CpuSSSE3:66:::RegXMM:Xmmword, + $mmx:CpuSSSE3::::RegMMX:Qword> -phaddw, 0x0f3801, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -phaddd, 0x0f3802, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -phaddsw, 0x0f3803, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -phsubw, 0x0f3805, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -phsubd, 0x0f3806, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -phsubsw, 0x0f3807, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -pmaddubsw, 0x0f3804, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -pmulhrsw, 0x0f380b, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -pshufb, 0x0f3800, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -psign, 0x0f3808 | , None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -psignd, 0x0f380a, None, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } -palignr, 0x0f3a0f, None, , Modrm|||NoSuf, { Imm8, ||Unspecified|BaseIndex, } -pabs, 0x0f381c | , None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } -pabsd, 0x0f381e, None, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +phaddw, 0x0f3801, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +phaddd, 0x0f3802, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +phaddsw, 0x0f3803, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +phsubw, 0x0f3805, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +phsubd, 0x0f3806, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +phsubsw, 0x0f3807, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +pmaddubsw, 0x0f3804, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +pmulhrsw, 0x0f380b, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +pshufb, 0x0f3800, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +psign, 0x0f3808 | , , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +psignd, 0x0f380a, , Modrm|||NoSuf, { ||Unspecified|BaseIndex, } +palignr, 0x0f3a0f, , Modrm|||NoSuf, { Imm8, ||Unspecified|BaseIndex, } +pabs, 0x0f381c | , , Modrm||NoSuf, { ||Unspecified|BaseIndex, } +pabsd, 0x0f381e, , Modrm||NoSuf, { ||Unspecified|BaseIndex, } // SSE4.1 instructions. -blendp, 0x660f3a0c | , None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -dpp, 0x660f3a40 | , None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -extractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } -extractps, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -extractps, 0x660f3a17, None, CpuSSE4_1|Cpu64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } -insertps, 0x660f3a21, None, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -movntdqa, 0x660f382a, None, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } -mpsadbw, 0x660f3a42, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -packusdw, 0x660f382b, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendw, 0x660f3a0e, None, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpeqq, 0x660f3829, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pextr, 0x660f3a14 | , None, , RegMem||NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } -pextr, 0x660f3a14 | , None, , Modrm||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } -pextrd, 0x660f3a16, None, , Modrm||NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } -pextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } -pextrq, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } -phminposuw, 0x660f3841, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pinsrb, 0x660f3a20, None, , Modrm|||NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } -pinsrb, 0x660f3a20, None, , Modrm|||NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } -pinsrd, 0x660f3a22, None, , Modrm|||NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } -pinsrq, 0x6622, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=1|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } -pinsrq, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } -pmaxsb, 0x660f383c, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxsd, 0x660f383d, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxud, 0x660f383f, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxuw, 0x660f383e, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminsb, 0x660f3838, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminsd, 0x660f3839, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminud, 0x660f383b, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminuw, 0x660f383a, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmovsxbw, 0x660f3820, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovsxbd, 0x660f3821, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovsxbq, 0x660f3822, None, , Modrm||NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovsxwd, 0x660f3823, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovsxwq, 0x660f3824, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovsxdq, 0x660f3825, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxbw, 0x660f3830, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxbd, 0x660f3831, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxbq, 0x660f3832, None, , Modrm||NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxwd, 0x660f3833, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxwq, 0x660f3834, None, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmovzxdq, 0x660f3835, None, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -pmuldq, 0x660f3828, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmulld, 0x660f3840, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -ptest, 0x660f3817, None, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -roundp, 0x660f3a08 | , None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -rounds, 0x660f3a0a | , None, , Modrm|||NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM } +blendp, 0x660f3a0c | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x660f3814 | , CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x660f3814 | , CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +dpp, 0x660f3a40 | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +extractps, 0x6617, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +extractps, 0x6617, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } +extractps, 0x660f3a17, CpuSSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +extractps, 0x660f3a17, CpuSSE4_1|Cpu64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } +insertps, 0x660f3a21, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +movntdqa, 0x660f382a, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } +mpsadbw, 0x660f3a42, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +packusdw, 0x660f382b, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x660f3810, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x660f3810, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendw, 0x660f3a0e, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpeqq, 0x660f3829, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pextr, 0x660f3a14 | , , RegMem||NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +pextr, 0x660f3a14 | , , Modrm||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +pextrd, 0x660f3a16, , Modrm||NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } +pextrq, 0x6616, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } +pextrq, 0x660f3a16, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } +phminposuw, 0x660f3841, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pinsrb, 0x660f3a20, , Modrm|||NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } +pinsrb, 0x660f3a20, , Modrm|||NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } +pinsrd, 0x660f3a22, , Modrm|||NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } +pinsrq, 0x6622, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=1|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } +pinsrq, 0x660f3a22, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } +pmaxsb, 0x660f383c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmaxsd, 0x660f383d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmaxud, 0x660f383f, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmaxuw, 0x660f383e, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminsb, 0x660f3838, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminsd, 0x660f3839, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminud, 0x660f383b, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pminuw, 0x660f383a, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmovsxbw, 0x660f3820, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovsxbd, 0x660f3821, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovsxbq, 0x660f3822, , Modrm||NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovsxwd, 0x660f3823, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovsxwq, 0x660f3824, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovsxdq, 0x660f3825, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxbw, 0x660f3830, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxbd, 0x660f3831, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxbq, 0x660f3832, , Modrm||NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxwd, 0x660f3833, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxwq, 0x660f3834, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmovzxdq, 0x660f3835, , Modrm||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +pmuldq, 0x660f3828, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pmulld, 0x660f3840, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +ptest, 0x660f3817, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +roundp, 0x660f3a08 | , , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +rounds, 0x660f3a0a | , , Modrm|||NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM } // SSE4.2 instructions. -pcmpgtq, 0x660f3837, None, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestri, 0x660f3a61, None, |CpuNo64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestri, 0x6661, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestri, 0x660f3a61, None, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestrm, 0x660f3a60, None, |CpuNo64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestrm, 0x6660, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestrm, 0x660f3a60, None, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpistri, 0x660f3a63, None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpistrm, 0x660f3a62, None, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -crc32, 0xf20f38f0, None, CpuSSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } -crc32, 0xf20f38f0, None, CpuSSE4_2|Cpu64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } +pcmpgtq, 0x660f3837, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpestri, 0x660f3a61, |CpuNo64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpestri, 0x6661, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestri, 0x660f3a61, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestrm, 0x660f3a60, |CpuNo64, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpestrm, 0x6660, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestrm, 0x660f3a60, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpistri, 0x660f3a63, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpistrm, 0x660f3a62, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +crc32, 0xf20f38f0, CpuSSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +crc32, 0xf20f38f0, CpuSSE4_2|Cpu64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } // xsave/xrstor New Instructions. -xsave, 0xfae, 4, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsave64, 0xfae, 4, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xrstor, 0xfae, 5, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xrstor64, 0xfae, 5, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xgetbv, 0xf01d0, None, CpuXsave, NoSuf, {} -xsetbv, 0xf01d1, None, CpuXsave, NoSuf, {} +xsave, 0xfae/4, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xsave64, 0xfae/4, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xrstor, 0xfae/5, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xrstor64, 0xfae/5, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xgetbv, 0xf01d0, CpuXsave, NoSuf, {} +xsetbv, 0xf01d1, CpuXsave, NoSuf, {} // xsaveopt -xsaveopt, 0xfae, 6, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsaveopt64, 0xfae, 6, CpuXsaveopt|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsaveopt, 0xfae/6, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xsaveopt64, 0xfae/6, CpuXsaveopt|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // AES instructions. -aesdec, 0x660f38de, None, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesdeclast, 0x660f38df, None, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesenc, 0x660f38dc, None, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesenclast, 0x660f38dd, None, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesimc, 0x660f38db, None, CpuAES, Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aeskeygenassist, 0x660f3adf, None, CpuAES, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +aesdec, 0x660f38de, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesdeclast, 0x660f38df, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesenc, 0x660f38dc, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesenclast, 0x660f38dd, CpuAES, Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesimc, 0x660f38db, CpuAES, Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aeskeygenassist, 0x660f3adf, CpuAES, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } // VAES -vaesdec, 0x66de, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesdeclast, 0x66df, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesenc, 0x66dc, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesenclast, 0x66dd, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesdec, 0x66de, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesdeclast, 0x66df, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesenc, 0x66dc, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesenclast, 0x66dd, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } // PCLMUL -pclmulqdq, 0x660f3a44, None, CpuPCLMUL, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pclmullqlqdq, 0x660f3a44, 0x00, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmulhqlqdq, 0x660f3a44, 0x01, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmullqhqdq, 0x660f3a44, 0x10, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmulhqhqdq, 0x660f3a44, 0x11, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulqdq, 0x660f3a44, CpuPCLMUL, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pclmullqlqdq, 0x660f3a44/0x00, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulhqlqdq, 0x660f3a44/0x01, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmullqhqdq, 0x660f3a44/0x10, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulhqhqdq, 0x660f3a44/0x11, CpuPCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } // GFNI -gf2p8affineqb, 0x660f3ace, None, CpuGFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -gf2p8affineinvqb, 0x660f3acf, None, CpuGFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -gf2p8mulb, 0x660f38cf, None, CpuGFNI, Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8affineqb, 0x660f3ace, CpuGFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8affineinvqb, 0x660f3acf, CpuGFNI, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8mulb, 0x660f38cf, CpuGFNI, Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // AVX instructions. @@ -1464,366 +1463,366 @@ gf2p8mulb, 0x660f38cf, None, CpuGFNI, Modrm||NoSuf, { R x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + y:Vex256:ATTSyntax:RegYMM|Unspecified|BaseIndex> -vaddp, 0x58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vadds, 0x58, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaddsubpd, 0x66d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vaddsubps, 0xf2d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandnp, 0x55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandp, 0x54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } -vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } -vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcmpp, 0xc2, 0x, CpuAVX, Modrm||Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vcmps, 0xc2, 0x, CpuAVX, Modrm||VexLIG|Space0F|VexVVVV|VexWIG|NoSuf|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vcmpp, 0xc2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vcmps, 0xc2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcomis, 0x2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM } -vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtpd2dq, 0xf2e6, None, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } -vcvtpd2ps, 0x665a, None, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } -vcvtps2dq, 0x665b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvts2si, 0x2d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -vcvtsd2ss, 0xf25a, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } -vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtts2si, 0x2c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -vdivp, 0x5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vdivs, 0x5e, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdppd, 0x6641, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdpps, 0x6640, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vextractf128, 0x6619, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } -vextractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -vextractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } -vhaddpd, 0x667c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhaddps, 0xf27c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhsubpd, 0x667d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhsubps, 0xf27d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vinsertf128, 0x6618, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } -vinsertps, 0x6621, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vlddqu, 0xf2f0, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } -vmaskmovdqu, 0x66f7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } -vmaskmovp, 0x662e | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmaskmovp, 0x662c | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxp, 0x5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxs, 0x5f, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vminp, 0x5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmins, 0x5d, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vmovap, 0x28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vaddp, 0x58, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vadds, 0x58, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaddsubpd, 0x66d0, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vaddsubps, 0xf2d0, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vandnp, 0x55, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vandp, 0x54, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendp, 0x660c | , CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendvp, 0x664a | , CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vbroadcastf128, 0x661a, CpuAVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } +vbroadcastsd, 0x6619, CpuAVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +vbroadcastss, 0x6618, CpuAVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcmpp, 0xc2/0x, CpuAVX, Modrm||Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vcmps, 0xc2/0x, CpuAVX, Modrm||VexLIG|Space0F|VexVVVV|VexWIG|NoSuf|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vcmpp, 0xc2, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vcmps, 0xc2, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcomis, 0x2f, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM } +vcvtdq2pd, 0xf3e6, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtdq2pd, 0xf3e6, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vcvtdq2ps, 0x5b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtpd2dq, 0xf2e6, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } +vcvtpd2ps, 0x665a, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } +vcvtps2dq, 0x665b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtps2pd, 0x5a, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2pd, 0x5a, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vcvts2si, 0x2d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +vcvtsd2ss, 0xf25a, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcvtsi2s, 0x2a, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2s, 0x2a, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sd, 0xf35a, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcvttpd2dq, 0x66e6, CpuAVX, Modrm||Space0F|VexWIG|NoSuf|, { , RegXMM } +vcvttps2dq, 0xf35b, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtts2si, 0x2c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +vdivp, 0x5e, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vdivs, 0x5e, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vdppd, 0x6641, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vdpps, 0x6640, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vextractf128, 0x6619, CpuAVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +vextractps, 0x6617, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +vextractps, 0x6617, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } +vhaddpd, 0x667c, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhaddps, 0xf27c, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhsubpd, 0x667d, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhsubps, 0xf27d, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vinsertf128, 0x6618, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } +vinsertps, 0x6621, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vlddqu, 0xf2f0, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vldmxcsr, 0xae/2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } +vmaskmovdqu, 0x66f7, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } +vmaskmovp, 0x662e | , CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmaskmovp, 0x662c | , CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxp, 0x5f, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxs, 0x5f, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vminp, 0x5d, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmins, 0x5d, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vmovap, 0x28, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } // vmovd really shouldn't allow for 64bit operand (vmovq is the right // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated // by Intel AVX spec). To avoid extra template in gcc x86 backend and // support assembler for AMD64, we accept 64bit operand on vmovd so // that we can use one template for both SSE and AVX instructions. -vmovd, 0x666e, None, CpuAVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovd, 0x667e, None, CpuAVX|Cpu64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } -vmovddup, 0xf212, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovddup, 0xf212, None, CpuAVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } -vmovdqa, 0x666f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovdqu, 0xf36f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovhlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovhp, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovhp, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovlhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovlp, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovlp, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovmskp, 0x50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } -vmovntdq, 0x66e7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmovntdqa, 0x662a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vmovntp, 0x2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmovq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovq, 0x66d6, None, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } -vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex, RegXMM } -vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovshdup, 0xf316, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovsldup, 0xf312, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovup, 0x10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmpsadbw, 0x6642, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmulp, 0x59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmuls, 0x59, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vorp, 0x56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpabs, 0x661c | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpabsd, 0x661e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpackssdw, 0x666b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpacksswb, 0x6663, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpackusdw, 0x662b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpackuswb, 0x6667, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpadds, 0x66ec | , None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpadd, 0x66fc | , None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddd, 0x66fe, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddq, 0x66d4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddus, 0x66dc | , None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpalignr, 0x660f, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpand, 0x66db, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpandn, 0x66df, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpavg, 0x66e0 | (3 * ), None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendvb, 0x664c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendw, 0x660e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeq, 0x6674 | , None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeqd, 0x6676, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeqq, 0x6629, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpestri, 0x6661, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestri, 0x6661, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestrm, 0x6660, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestrm, 0x6660, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpgt, 0x6664 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpgtd, 0x6666, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpgtq, 0x6637, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpistri, 0x6663, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpistrm, 0x6662, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vperm2f128, 0x6606, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermilp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermilp, 0x6604 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexW0|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpextr, 0x6616, None, CpuAVX|, Modrm|Vex|Space0F3A||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } -vpextrw, 0x66c5, None, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr, 0x6614 | , None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr, 0x6614 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } -vphaddd, 0x6602, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddsw, 0x6603, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddw, 0x6601, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphminposuw, 0x6641, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } -vphsubd, 0x6606, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphsubsw, 0x6607, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphsubw, 0x6605, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsr, 0x6622, None, CpuAVX|, Modrm|Vex|Space0F3A|VexVVVV||NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmaddubsw, 0x6604, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaddwd, 0x66f5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsb, 0x663c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsd, 0x663d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsw, 0x66ee, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxub, 0x66de, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxud, 0x663f, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxuw, 0x663e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsb, 0x6638, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsd, 0x6639, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsw, 0x66ea, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminub, 0x66da, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminud, 0x663b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminuw, 0x663a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmovmskb, 0x66d7, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } -vpmovsxbd, 0x6621, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxbq, 0x6622, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxbw, 0x6620, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxdq, 0x6625, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxwd, 0x6623, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxwq, 0x6624, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbd, 0x6631, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbq, 0x6632, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbw, 0x6630, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxdq, 0x6635, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxwd, 0x6633, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxwq, 0x6634, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmuldq, 0x6628, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhrsw, 0x660b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhuw, 0x66e4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhw, 0x66e5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulld, 0x6640, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmullw, 0x66d5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmuludq, 0x66f4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpor, 0x66eb, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsadbw, 0x66f6, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpshufb, 0x6600, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpshufd, 0x6670, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshufhw, 0xf370, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshuflw, 0xf270, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpsign, 0x6608 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsignd, 0x660a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsll, 0x6672 | , 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsll, 0x66f2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpslldq, 0x6673, 7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllw, 0x6671, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllw, 0x66f1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrad, 0x6672, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrad, 0x66e2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsraw, 0x6671, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsraw, 0x66e1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrl, 0x6672 | , 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrl, 0x66d2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrldq, 0x6673, 3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlw, 0x6671, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlw, 0x66d1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsub, 0x66f8 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsub, 0x66fa | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubs, 0x66e8 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubus, 0x66d8 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vptest, 0x6617, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhbw, 0x6668, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhdq, 0x666a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhqdq, 0x666d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhwd, 0x6669, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklbw, 0x6660, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckldq, 0x6662, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklqdq, 0x666c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklwd, 0x6661, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpxor, 0x66ef, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vrcpps, 0x53, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrcpss, 0xf353, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vroundp, 0x6608 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrounds, 0x660a | , None, CpuAVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vrsqrtps, 0x52, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrsqrtss, 0xf352, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vshufp, 0xc6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsqrtp, 0x51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vsqrts, 0x51, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } -vsubp, 0x5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsubs, 0x5c, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vtestp, 0x660e | , None, CpuAVX, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vucomis, 0x2e, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM } -vunpckhp, 0x15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vunpcklp, 0x14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vxorp, 0x57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vzeroall, 0x77, None, CpuAVX, Vex=2|Space0F|VexWIG|NoSuf, {} -vzeroupper, 0x77, None, CpuAVX, Vex|Space0F|VexWIG|NoSuf, {} +vmovd, 0x666e, CpuAVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +vmovd, 0x667e, CpuAVX|Cpu64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } +vmovddup, 0xf212, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovddup, 0xf212, CpuAVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } +vmovdqa, 0x666f, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovdqu, 0xf36f, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovhlps, 0x12, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovhp, 0x16, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovhp, 0x17, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovlhps, 0x16, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovlp, 0x12, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovlp, 0x13, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovmskp, 0x50, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } +vmovntdq, 0x66e7, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmovntdqa, 0x662a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vmovntp, 0x2b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmovq, 0xf37e, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovq, 0x66d6, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vmovq, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } +vmovs, 0x10, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex, RegXMM } +vmovs, 0x10, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovshdup, 0xf316, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovsldup, 0xf312, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovup, 0x10, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmpsadbw, 0x6642, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmulp, 0x59, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmuls, 0x59, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vorp, 0x56, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpabs, 0x661c | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpabsd, 0x661e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpackssdw, 0x666b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpacksswb, 0x6663, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpackusdw, 0x662b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpackuswb, 0x6667, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpadds, 0x66ec | , CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpadd, 0x66fc | , CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddd, 0x66fe, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddq, 0x66d4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddus, 0x66dc | , CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpalignr, 0x660f, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpand, 0x66db, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpandn, 0x66df, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpavg, 0x66e0 | (3 * ), CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendvb, 0x664c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendw, 0x660e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeq, 0x6674 | , CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeqd, 0x6676, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeqq, 0x6629, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpestri, 0x6661, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestri, 0x6661, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestrm, 0x6660, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestrm, 0x6660, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpgt, 0x6664 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpgtd, 0x6666, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpgtq, 0x6637, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpistri, 0x6663, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpistrm, 0x6662, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vperm2f128, 0x6606, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermilp, 0x660c | , CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermilp, 0x6604 | , CpuAVX, Modrm|Vex|Space0F3A|VexW0|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpextr, 0x6616, CpuAVX|, Modrm|Vex|Space0F3A||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +vpextrw, 0x66c5, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr, 0x6614 | , CpuAVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr, 0x6614 | , CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +vphaddd, 0x6602, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddsw, 0x6603, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddw, 0x6601, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphminposuw, 0x6641, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } +vphsubd, 0x6606, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphsubsw, 0x6607, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphsubw, 0x6605, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpinsrb, 0x6620, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrb, 0x6620, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsr, 0x6622, CpuAVX|, Modrm|Vex|Space0F3A|VexVVVV||NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsrw, 0x66c4, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrw, 0x66c4, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmaddubsw, 0x6604, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaddwd, 0x66f5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsb, 0x663c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsd, 0x663d, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsw, 0x66ee, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxub, 0x66de, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxud, 0x663f, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxuw, 0x663e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsb, 0x6638, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsd, 0x6639, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsw, 0x66ea, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminub, 0x66da, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminud, 0x663b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminuw, 0x663a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmovmskb, 0x66d7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } +vpmovsxbd, 0x6621, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxbq, 0x6622, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxbw, 0x6620, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxdq, 0x6625, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxwd, 0x6623, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxwq, 0x6624, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbd, 0x6631, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbq, 0x6632, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbw, 0x6630, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxdq, 0x6635, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxwd, 0x6633, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxwq, 0x6634, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmuldq, 0x6628, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhrsw, 0x660b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhuw, 0x66e4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhw, 0x66e5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulld, 0x6640, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmullw, 0x66d5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmuludq, 0x66f4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpor, 0x66eb, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsadbw, 0x66f6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpshufb, 0x6600, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpshufd, 0x6670, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshufhw, 0xf370, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshuflw, 0xf270, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpsign, 0x6608 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsignd, 0x660a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll, 0x6672 | /6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll, 0x66f2 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpslldq, 0x6673/7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllw, 0x6671/6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllw, 0x66f1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrad, 0x6672/4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrad, 0x66e2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsraw, 0x6671/4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsraw, 0x66e1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl, 0x6672 | /2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl, 0x66d2 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrldq, 0x6673/3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlw, 0x6671/2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlw, 0x66d1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsub, 0x66f8 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsub, 0x66fa | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsubs, 0x66e8 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsubus, 0x66d8 | , CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vptest, 0x6617, CpuAVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhbw, 0x6668, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhdq, 0x666a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhqdq, 0x666d, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhwd, 0x6669, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklbw, 0x6660, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckldq, 0x6662, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklqdq, 0x666c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklwd, 0x6661, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpxor, 0x66ef, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vrcpps, 0x53, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrcpss, 0xf353, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vroundp, 0x6608 | , CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrounds, 0x660a | , CpuAVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vrsqrtps, 0x52, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrsqrtss, 0xf352, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vshufp, 0xc6, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsqrtp, 0x51, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vsqrts, 0x51, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vstmxcsr, 0xae/3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } +vsubp, 0x5c, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsubs, 0x5c, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vtestp, 0x660e | , CpuAVX, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vucomis, 0x2e, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM } +vunpckhp, 0x15, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vunpcklp, 0x14, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vxorp, 0x57, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vzeroall, 0x77, CpuAVX, Vex=2|Space0F|VexWIG|NoSuf, {} +vzeroupper, 0x77, CpuAVX, Vex|Space0F|VexWIG|NoSuf, {} // 256bit integer AVX2 instructions. -vpmovsxbd, 0x6621, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxbq, 0x6622, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxbw, 0x6620, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxdq, 0x6625, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxwd, 0x6623, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxwq, 0x6624, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbd, 0x6631, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbq, 0x6632, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbw, 0x6630, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxdq, 0x6635, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxwd, 0x6633, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxwq, 0x6634, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbd, 0x6621, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbq, 0x6622, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbw, 0x6620, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxdq, 0x6625, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxwd, 0x6623, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxwq, 0x6624, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbd, 0x6631, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbq, 0x6632, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbw, 0x6630, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxdq, 0x6635, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxwd, 0x6633, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxwq, 0x6634, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } // New AVX2 instructions. -vbroadcasti128, 0x665A, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } -vbroadcastsd, 0x6619, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } -vbroadcastss, 0x6618, None, CpuAVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } -vpblendd, 0x6602, None, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpbroadcast, 0x6678 | , None, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } -vpbroadcast, 0x6658 | , None, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } -vperm2i128, 0x6646, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermd, 0x6636, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermpd, 0x6601, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } -vpermps, 0x6616, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermq, 0x6600, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } -vextracti128, 0x6639, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } -vinserti128, 0x6638, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } -vpmaskmov, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vpmaskmov, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllv, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsravd, 0x6646, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlv, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vbroadcasti128, 0x665A, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } +vbroadcastsd, 0x6619, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } +vbroadcastss, 0x6618, CpuAVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } +vpblendd, 0x6602, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpbroadcast, 0x6678 | , CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } +vpbroadcast, 0x6658 | , CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } +vperm2i128, 0x6646, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermd, 0x6636, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermpd, 0x6601, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vpermps, 0x6616, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermq, 0x6600, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vextracti128, 0x6639, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +vinserti128, 0x6638, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } +vpmaskmov, 0x668e, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vpmaskmov, 0x668c, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllv, 0x6647, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsravd, 0x6646, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlv, 0x6645, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX gather instructions -vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||NoSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||NoSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp, 0x6693, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||NoSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq, 0x6691, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||NoSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } // AES + AVX -vaesdec, 0x66de, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesdeclast, 0x66df, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesenc, 0x66dc, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesenclast, 0x66dd, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesimc, 0x66db, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } -vaeskeygenassist, 0x66df, None, CpuAVX|CpuAES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vaesdec, 0x66de, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesdeclast, 0x66df, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesenc, 0x66dc, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesenclast, 0x66dd, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesimc, 0x66db, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } +vaeskeygenassist, 0x66df, CpuAVX|CpuAES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } // PCLMUL + AVX -vpclmulqdq, 0x6644, None, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmullqlqdq, 0x6644, 0x00, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmulhqlqdq, 0x6644, 0x01, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmullqhqdq, 0x6644, 0x10, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmulhqhqdq, 0x6644, 0x11, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulqdq, 0x6644, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmullqlqdq, 0x6644/0x00, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulhqlqdq, 0x6644/0x01, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmullqhqdq, 0x6644/0x10, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulhqhqdq, 0x6644/0x11, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // GFNI + AVX -vgf2p8affineinvqb, 0x66cf, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vgf2p8affineqb, 0x66ce, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vgf2p8mulb, 0x66cf, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8affineinvqb, 0x66cf, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8affineqb, 0x66ce, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8mulb, 0x66cf, CpuAVX|CpuGFNI, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // FSGSBASE, RDRND and F16C -rdfsbase, 0xf30fae, 0, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -rdgsbase, 0xf30fae, 1, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -rdrand, 0xfc7, 6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } -wrfsbase, 0xf30fae, 2, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -wrgsbase, 0xf30fae, 3, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -vcvtph2ps, 0x6613, None, CpuF16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vcvtph2ps, 0x6613, None, CpuF16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vcvtps2ph, 0x661d, None, CpuF16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vcvtps2ph, 0x661d, None, CpuF16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +rdfsbase, 0xf30fae/0, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +rdgsbase, 0xf30fae/1, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +rdrand, 0xfc7/6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } +wrfsbase, 0xf30fae/2, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +wrgsbase, 0xf30fae/3, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +vcvtph2ps, 0x6613, CpuF16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vcvtph2ps, 0x6613, CpuF16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vcvtps2ph, 0x661d, CpuF16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vcvtps2ph, 0x661d, CpuF16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } // FMA instructions -vfmaddp, 0x6688 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadds, 0x6689 | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmaddsubp, 0x6686 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubp, 0x668a | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubs, 0x668b | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmsubaddp, 0x6687 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmaddp, 0x668c | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadds, 0x668d | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfnmsubp, 0x668e | 0x, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubs, 0x668f | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6688 | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds, 0x6689 | 0x, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubp, 0x668a | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs, 0x668b | 0x, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmaddp, 0x668c | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds, 0x668d | 0x, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, CpuFMA, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs, 0x668f | 0x, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV||NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // HLE prefixes -xacquire, 0xf2, None, CpuHLE, NoSuf|IsPrefix, {} -xrelease, 0xf3, None, CpuHLE, NoSuf|IsPrefix, {} +xacquire, 0xf2, CpuHLE, NoSuf|IsPrefix, {} +xrelease, 0xf3, CpuHLE, NoSuf|IsPrefix, {} // RTM instructions -xabort, 0xc6f8, None, CpuRTM, NoSuf, { Imm8 } -xbegin, 0xc7f8, None, CpuRTM, JumpDword|NoSuf, { Disp16|Disp32 } -xend, 0xf01d5, None, CpuRTM, NoSuf, {} -xtest, 0xf01d6, None, CpuHLE|CpuRTM, NoSuf, {} +xabort, 0xc6f8, CpuRTM, NoSuf, { Imm8 } +xbegin, 0xc7f8, CpuRTM, JumpDword|NoSuf, { Disp16|Disp32 } +xend, 0xf01d5, CpuRTM, NoSuf, {} +xtest, 0xf01d6, CpuHLE|CpuRTM, NoSuf, {} // BMI2 instructions. -bzhi, 0xf5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -mulx, 0xf2f6, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -pdep, 0xf2f5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -pext, 0xf3f5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -rorx, 0xf2f0, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -sarx, 0xf3f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -shlx, 0x66f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -shrx, 0xf2f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +bzhi, 0xf5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +mulx, 0xf2f6, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pdep, 0xf2f5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pext, 0xf3f5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +rorx, 0xf2f0, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +sarx, 0xf3f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +shlx, 0x66f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +shrx, 0xf2f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } // FMA4 instructions -vfmaddp, 0x6668 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadds, 0x666a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubp, 0x665c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubaddp, 0x665e | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubp, 0x666c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubs, 0x666e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddp, 0x6678 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadds, 0x667a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubp, 0x667c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubs, 0x667e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6668 | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds, 0x666a | , CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x665c | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubaddp, 0x665e | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubp, 0x666c | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs, 0x666e | , CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddp, 0x6678 | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds, 0x667a | , CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x667c | , CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs, 0x667e | , CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } // XOP instructions @@ -1831,41 +1830,41 @@ vfnmsubs, 0x667e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV -vfrczp, 0x80 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vfrczs, 0x82 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { |RegXMM|Unspecified|BaseIndex, RegXMM } -vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcom, 0xcc | 0x | , None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpcom, 0xcc | 0x | , , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddb, 0xc2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadddq, 0xcb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddub, 0xd2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddubw, 0xd1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddudq, 0xdb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadduw, 0xd6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddw, 0xc6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubbw, 0xe1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubdq, 0xe3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubwd, 0xe2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vpmacsdd, 0x9e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdqh, 0x9f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdql, 0x97, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdd, 0x8e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdqh, 0x8f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdql, 0x87, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsswd, 0x86, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssww, 0x85, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacswd, 0x96, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsww, 0x95, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vprot, 0x90 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vprot, 0xc0 | , None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -vpsha, 0x98 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vpshl, 0x94 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vfrczp, 0x80 | , CpuXOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vfrczs, 0x82 | , CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { |RegXMM|Unspecified|BaseIndex, RegXMM } +vpcmov, 0xa2, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcom, 0xcc | 0x | , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpcom, 0xcc | 0x | /, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpermil2p, 0x6648 | , CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddb, 0xc2 | , CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddbw, 0xc1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphadddq, 0xcb, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddub, 0xd2 | , CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddubw, 0xd1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddudq, 0xdb, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphadduw, 0xd6 | , CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddw, 0xc6 | , CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubbw, 0xe1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubdq, 0xe3, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubwd, 0xe2, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vpmacsdd, 0x9e, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 0x9f, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 0x97, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 0x8e, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 0x8f, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 0x87, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 0x86, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 0x85, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 0x96, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 0x95, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 0xa6, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 0xb6, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 0xa3, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vprot, 0x90 | , CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vprot, 0xc0 | , CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +vpsha, 0x98 | , CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vpshl, 0x94 | , CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1873,160 +1872,160 @@ vpshl, 0x94 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexS // LWP instructions -llwpcb, 0x12, 0, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } -slwpcb, 0x12, 1, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } -lwpval, 0x12, 1, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -lwpins, 0x12, 0, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +llwpcb, 0x12/0, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } +slwpcb, 0x12/1, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } +lwpval, 0x12/1, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +lwpins, 0x12/0, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } // BMI instructions -andn, 0xf2, None, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -bextr, 0xf7, None, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsi, 0xf3, 3, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsmsk, 0xf3, 2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsr, 0xf3, 1, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -tzcnt, 0xf30fbc, None, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +andn, 0xf2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +bextr, 0xf7, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsi, 0xf3/3, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsmsk, 0xf3/2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsr, 0xf3/1, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +tzcnt, 0xf30fbc, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // TBM instructions -bextr, 0x10, None, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP0A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcfill, 0x01, 1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blci, 0x02, 6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcic, 0x01, 5, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcmsk, 0x02, 1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcs, 0x01, 3, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsfill, 0x01, 2, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsic, 0x01, 6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -t1mskc, 0x01, 7, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -tzmsk, 0x01, 4, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +bextr, 0x10, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP0A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcfill, 0x01/1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blci, 0x02/6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcic, 0x01/5, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcmsk, 0x02/1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcs, 0x01/3, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsfill, 0x01/2, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsic, 0x01/6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +t1mskc, 0x01/7, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +tzmsk, 0x01/4, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } // AMD 3DNow! instructions. -prefetch, 0xf0d, 0, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetchw, 0xf0d, 1, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -femms, 0xf0e, None, Cpu3dnow, NoSuf, {} -pavgusb, 0xf0f, 0xbf, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pf2id, 0xf0f, 0x1d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pf2iw, 0xf0f, 0x1c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfacc, 0xf0f, 0xae, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfadd, 0xf0f, 0x9e, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpeq, 0xf0f, 0xb0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpge, 0xf0f, 0x90, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpgt, 0xf0f, 0xa0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmax, 0xf0f, 0xa4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmin, 0xf0f, 0x94, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmul, 0xf0f, 0xb4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfnacc, 0xf0f, 0x8a, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfpnacc, 0xf0f, 0x8e, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcp, 0xf0f, 0x96, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcpit1, 0xf0f, 0xa6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcpit2, 0xf0f, 0xb6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrsqit1, 0xf0f, 0xa7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrsqrt, 0xf0f, 0x97, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfsub, 0xf0f, 0x9a, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfsubr, 0xf0f, 0xaa, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pi2fd, 0xf0f, 0x0d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pi2fw, 0xf0f, 0x0c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pmulhrw, 0xf0f, 0xb7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pswapd, 0xf0f, 0xbb, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +prefetch, 0xf0d/0, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchw, 0xf0d/1, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +femms, 0xf0e, Cpu3dnow, NoSuf, {} +pavgusb, 0xf0f/0xbf, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pf2id, 0xf0f/0x1d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pf2iw, 0xf0f/0x1c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfacc, 0xf0f/0xae, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfadd, 0xf0f/0x9e, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpeq, 0xf0f/0xb0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpge, 0xf0f/0x90, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpgt, 0xf0f/0xa0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmax, 0xf0f/0xa4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmin, 0xf0f/0x94, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmul, 0xf0f/0xb4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfnacc, 0xf0f/0x8a, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfpnacc, 0xf0f/0x8e, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcp, 0xf0f/0x96, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcpit1, 0xf0f/0xa6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcpit2, 0xf0f/0xb6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrsqit1, 0xf0f/0xa7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrsqrt, 0xf0f/0x97, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfsub, 0xf0f/0x9a, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfsubr, 0xf0f/0xaa, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pi2fd, 0xf0f/0x0d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pi2fw, 0xf0f/0x0c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmulhrw, 0xf0f/0xb7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pswapd, 0xf0f/0xbb, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } // AMD extensions. -syscall, 0xf05, None, CpuSYSCALL, NoSuf, {} -sysret, 0xf07, None, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf, {} -swapgs, 0xf01f8, None, Cpu64, NoSuf, {} -rdtscp, 0xf01f9, None, CpuRdtscp, NoSuf, {} +syscall, 0xf05, CpuSYSCALL, NoSuf, {} +sysret, 0xf07, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf, {} +swapgs, 0xf01f8, Cpu64, NoSuf, {} +rdtscp, 0xf01f9, CpuRdtscp, NoSuf, {} // AMD Pacifica additions. -clgi, 0xf01dd, None, CpuSVME, NoSuf, {} -invlpga, 0xf01df, None, CpuSVME, NoSuf, {} -invlpga, 0xf01df, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } -skinit, 0xf01de, None, CpuSVME, NoSuf, {} -skinit, 0xf01de, None, CpuSVME, IgnoreSize|NoSuf, { Acc|Dword } -stgi, 0xf01dc, None, CpuSVME, NoSuf, {} -vmgexit, 0xf30f01d9, None, CpuSEV_ES, NoSuf, {} -vmload, 0xf01da, None, CpuSVME, NoSuf, {} -vmload, 0xf01da, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -vmmcall, 0xf01d9, None, CpuSVME, NoSuf, {} -vmrun, 0xf01d8, None, CpuSVME, NoSuf, {} -vmrun, 0xf01d8, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -vmsave, 0xf01db, None, CpuSVME, NoSuf, {} -vmsave, 0xf01db, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +clgi, 0xf01dd, CpuSVME, NoSuf, {} +invlpga, 0xf01df, CpuSVME, NoSuf, {} +invlpga, 0xf01df, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } +skinit, 0xf01de, CpuSVME, NoSuf, {} +skinit, 0xf01de, CpuSVME, IgnoreSize|NoSuf, { Acc|Dword } +stgi, 0xf01dc, CpuSVME, NoSuf, {} +vmgexit, 0xf30f01d9, CpuSEV_ES, NoSuf, {} +vmload, 0xf01da, CpuSVME, NoSuf, {} +vmload, 0xf01da, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +vmmcall, 0xf01d9, CpuSVME, NoSuf, {} +vmrun, 0xf01d8, CpuSVME, NoSuf, {} +vmrun, 0xf01d8, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +vmsave, 0xf01db, CpuSVME, NoSuf, {} +vmsave, 0xf01db, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } // SSE4a instructions -movntsd, 0xf20f2b, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -movntss, 0xf30f2b, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -extrq, 0x660f78, 0, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } -extrq, 0x660f79, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } -insertq, 0xf20f79, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } -insertq, 0xf20f78, None, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } +movntsd, 0xf20f2b, CpuSSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +movntss, 0xf30f2b, CpuSSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +extrq, 0x660f78/0, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } +extrq, 0x660f79, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } +insertq, 0xf20f79, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } +insertq, 0xf20f78, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } // LZCNT instruction -lzcnt, 0xf30fbd, None, CpuLZCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lzcnt, 0xf30fbd, CpuLZCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // POPCNT instruction -popcnt, 0xf30fb8, None, CpuPOPCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +popcnt, 0xf30fb8, CpuPOPCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // VIA PadLock extensions. -xstore-rng, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ecb, 0xf30fa7c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-cbc, 0xf30fa7d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ctr, 0xf30fa7d8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-cfb, 0xf30fa7e0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ofb, 0xf30fa7e8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -montmul, 0xf30fa6c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xsha1, 0xf30fa6c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xsha256, 0xf30fa6d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} +xstore-rng, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcrypt-ecb, 0xf30fa7c8, CpuPadLock, NoSuf|RepPrefixOk, {} +xcrypt-cbc, 0xf30fa7d0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcrypt-ctr, 0xf30fa7d8, CpuPadLock, NoSuf|RepPrefixOk, {} +xcrypt-cfb, 0xf30fa7e0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcrypt-ofb, 0xf30fa7e8, CpuPadLock, NoSuf|RepPrefixOk, {} +montmul, 0xf30fa6c0, CpuPadLock, NoSuf|RepPrefixOk, {} +xsha1, 0xf30fa6c8, CpuPadLock, NoSuf|RepPrefixOk, {} +xsha256, 0xf30fa6d0, CpuPadLock, NoSuf|RepPrefixOk, {} // Aliases without hyphens. -xstorerng, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptecb, 0xf30fa7c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptcbc, 0xf30fa7d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptctr, 0xf30fa7d8, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptcfb, 0xf30fa7e0, None, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptofb, 0xf30fa7e8, None, CpuPadLock, NoSuf|RepPrefixOk, {} +xstorerng, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcryptecb, 0xf30fa7c8, CpuPadLock, NoSuf|RepPrefixOk, {} +xcryptcbc, 0xf30fa7d0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcryptctr, 0xf30fa7d8, CpuPadLock, NoSuf|RepPrefixOk, {} +xcryptcfb, 0xf30fa7e0, CpuPadLock, NoSuf|RepPrefixOk, {} +xcryptofb, 0xf30fa7e8, CpuPadLock, NoSuf|RepPrefixOk, {} // Alias for xstore-rng. -xstore, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} +xstore, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} // Multy-precision Add Carry, rdseed instructions. -adcx, 0x660f38f6, None, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -adox, 0xf30f38f6, None, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -rdseed, 0xfc7, 7, CpuRdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } +adcx, 0x660f38f6, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adox, 0xf30f38f6, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +rdseed, 0xfc7/7, CpuRdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } // SMAP instructions. -clac, 0xf01ca, None, CpuSMAP, NoSuf, {} -stac, 0xf01cb, None, CpuSMAP, NoSuf, {} +clac, 0xf01ca, CpuSMAP, NoSuf, {} +stac, 0xf01cb, CpuSMAP, NoSuf, {} // BND prefix -bnd, 0xf2, None, CpuMPX, NoSuf|IsPrefix, {} +bnd, 0xf2, CpuMPX, NoSuf|IsPrefix, {} // MPX instructions. -bndmk, 0xf30f1b, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } -bndmov, 0x660f1a, None, CpuMPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } -bndcl, 0xf30f1a, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcl, 0xf30f1a, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndcu, 0xf20f1a, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcu, 0xf20f1a, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndcn, 0xf20f1b, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcn, 0xf20f1b, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndstx, 0x0f1b, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } -bndldx, 0x0f1a, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } +bndmk, 0xf30f1b, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } +bndmov, 0x660f1a, CpuMPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } +bndcl, 0xf30f1a, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcl, 0xf30f1a, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndcu, 0xf20f1a, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcu, 0xf20f1a, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndcn, 0xf20f1b, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcn, 0xf20f1b, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndstx, 0x0f1b, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } +bndldx, 0x0f1a, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } // SHA instructions. -sha1rnds4, 0xf3acc, None, CpuSHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -sha1nexte, 0xf38c8, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha1msg1, 0xf38c9, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha1msg2, 0xf38ca, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256rnds2, 0xf38cb, None, CpuSHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -sha256rnds2, 0xf38cb, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256msg1, 0xf38cc, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256msg2, 0xf38cd, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1rnds4, 0xf3acc, CpuSHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +sha1nexte, 0xf38c8, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg1, 0xf38c9, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg2, 0xf38ca, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xf38cb, CpuSHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xf38cb, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg1, 0xf38cc, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg2, 0xf38cd, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // VPCLMULQDQ instructions -vpclmulqdq, 0x6644, None, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmullqlqdq, 0x6644, 0x00, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmulhqlqdq, 0x6644, 0x01, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmullqhqdq, 0x6644, 0x10, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulqdq, 0x6644, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmullqlqdq, 0x6644/0x00, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulhqlqdq, 0x6644/0x01, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmullqhqdq, 0x6644/0x10, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulhqhqdq, 0x6644/0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } // VPCLMULQDQ instructions end @@ -2048,657 +2047,657 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV x:CpuAVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, + y:CpuAVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM> -kand, 0x41, None, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -kandn, 0x42, None, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -kor, 0x45, None, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -kxnor, 0x46, None, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -kxor, 0x47, None, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kand, 0x41, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kandn, 0x42, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kor, 0x45, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kxnor, 0x46, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kxor, 0x47, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -kmov, 0x90, None, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } -kmov, 0x91, None, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } -kmov, 0x92, None, , D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } +kmov, 0x90, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x91, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0x92, , D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } -knot, 0x44, None, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } -kortest, 0x98, None, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } +knot, 0x44, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } +kortest, 0x98, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } -kshiftl, 0x6632, None, , Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } -kshiftr, 0x6630, None, , Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } +kshiftl, 0x6632, , Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } +kshiftr, 0x6630, , Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } -kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } +kunpckbw, 0x664B, CpuAVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } -vaddp, 0x58, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vdivp, 0x5e, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmulp, 0x59, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vsqrtp, 0x51, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vsubp, 0x5c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaddp, 0x58, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdivp, 0x5e, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmulp, 0x59, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vsqrtp, 0x51, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vsubp, 0x5c, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vadds, 0x58, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vdivs, 0x5e, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vmuls, 0x59, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vadds, 0x58, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vdivs, 0x5e, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vmuls, 0x59, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsqrts, 0x51, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsubs, 0x5C, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -valign, 0x6603, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpblendm, 0x6664, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2, 0x6676, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2, 0x667E, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxs, 0x663D, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxu, 0x663F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmins, 0x6639, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminu, 0x663B, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolv, 0x6615, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorv, 0x6614, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllv, 0x6647, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrav, 0x6646, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlv, 0x6645, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlog, 0x6625, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +valign, 0x6603, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vblendmp, 0x6665, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpblendm, 0x6664, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2, 0x6676, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2p, 0x6677, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667E, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2p, 0x667F, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxs, 0x663D, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxu, 0x663F, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmins, 0x6639, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminu, 0x663B, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuldq, 0x6628, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulld, 0x6640, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprolv, 0x6615, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprorv, 0x6614, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllv, 0x6647, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrav, 0x6646, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlv, 0x6645, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog, 0x6625, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastf32x4, 0x661A, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti32x4, 0x665A, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcastf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti64x4, 0x665B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcastf64x4, 0x661B, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti64x4, 0x665B, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastss, 0x6618, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcastsd, 0x6619, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpbroadcast, 0x6658 | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x667c, None, CpuAVX512F, Modrm|Masking=3|Space0F38||NoSuf, { , RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x6658 | , CpuAVX512F, Modrm|Masking=3|Space0F38||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x667c, CpuAVX512F, Modrm|Masking=3|Space0F38||NoSuf, { , RegXMM|RegYMM|RegZMM } -vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp, 0xC2/0x, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp, 0xC2, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmps, 0xC2, 0x, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } -vcmps, 0xC2, None, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2/0x, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } -vcomis, 0x2f, None, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } -vucomis, 0x2e, None, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } +vcomis, 0x2f, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } +vucomis, 0x2e, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } -vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressq, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressd, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompresspd, 0x668A, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompressps, 0x668A, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressq, 0x668B, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressd, 0x668B, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vscatterqpd, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vpscatterqd, 0x66A1, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } +vscatterqpd, 0x66A3, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vcvtdq2pd, 0xF3E6, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtdq2pd, 0xF3E6, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtudq2pd, 0xF37A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtdq2ps, 0x5B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2udq, 0x79, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2dq, 0xf2e6, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvtpd2ps, 0x665a, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2ps, 0x665a, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvtpd2udq, 0x79, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2udq, 0x79, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } +vcvtph2ps, 0x6613, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } -vcvtps2dq, 0x665B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2dq, 0x665B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2pd, 0x5A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2pd, 0x5A, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2ph, 0x661D, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vcvts2si, 0x2d, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvts2usi, 0x79, None, , Modrm|EVexLIG||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } +vcvts2si, 0x2d, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } +vcvts2usi, 0x79, , Modrm|EVexLIG||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvtsd2ss, 0xF25A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2ss, 0xF25A, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2ss, 0xF32A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2ss, 0xF32A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 0xF32A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 0xF32A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 0xF37B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 0xF37B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sd, 0xF35A, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvttpd2udq, 0x78, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvttpd2dq, 0x66e6, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvttpd2udq, 0x78, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2dq, 0xF35B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2udq, 0x78, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtts2si, 0x2c, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvtts2usi, 0x78, None, , Modrm|EVexLIG||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } +vcvtts2si, 0x2c, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } +vcvtts2usi, 0x78, , Modrm|EVexLIG||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvtudq2ps, 0xF27A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtudq2ps, 0xF27A, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandpd, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandq, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandpd, 0x6688, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandq, 0x6689, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandps, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandd, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandps, 0x6688, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandd, 0x6689, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vextractf32x4, 0x6619, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti32x4, 0x6639, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextractf32x4, 0x6619, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti32x4, 0x6639, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextractf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextractf64x4, 0x661B, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti64x4, 0x663B, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } +vextractps, 0x6617, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +vextractps, 0x6617, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } -vfixupimmp, 0x6654, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfixupimms, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfixupimmp, 0x6654, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfixupimms, 0x6655, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vgetmantp, 0x26, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetmants, 0x27, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vgetmantp, 0x26, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetmants, 0x27, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrndscalep, 0x08 | , None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrndscales, 0x0a | , None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrndscalep, 0x08 | , , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrndscales, 0x0a | , , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddp, 0x6688 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmadds, 0x6689 | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddsubp, 0x6686 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubp, 0x668a | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubs, 0x668b | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmsubaddp, 0x6687 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmaddp, 0x668c | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmadds, 0x668d | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfnmsubp, 0x668e | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmsubs, 0x668f | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddp, 0x6688 | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmadds, 0x6689 | 0x, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubp, 0x668a | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubs, 0x668b | 0x, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmaddp, 0x668c | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmadds, 0x668d | 0x, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmsubs, 0x668f | 0x, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vscalefp, 0x662c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vscalefs, 0x662d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vscalefp, 0x662c, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vscalefs, 0x662d, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vgatherdpd, 0x6692, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherdps, 0x6692, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vgatherqpd, 0x6693, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherqps, 0x6693, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdd, 0x6690, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vpgatherdq, 0x6690, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vpgatherqd, 0x6691, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherqq, 0x6691, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherdpd, 0x6692, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherdps, 0x6692, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } +vgatherqpd, 0x6693, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherqps, 0x6693, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdd, 0x6690, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } +vpgatherdq, 0x6690, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vpgatherqd, 0x6691, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherqq, 0x6691, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vmovntdqa, 0x662A, None, CpuAVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntdqa, 0x662A, CpuAVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetexpp, 0x6642, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetexps, 0x6643, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vgetexpp, 0x6642, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetexps, 0x6643, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vinsertf32x4, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti32x4, 0x6638, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinsertf32x4, 0x6618, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti32x4, 0x6638, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinsertf64x4, 0x661A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti64x4, 0x663A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinsertf64x4, 0x661A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti64x4, 0x663A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinsertps, 0x6621, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vinsertps, 0x6621, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmaxp, 0x5f, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmaxs, 0x5f, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vmaxp, 0x5f, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmaxs, 0x5f, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vminp, 0x5d, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmins, 0x5d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vminp, 0x5d, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmins, 0x5d, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vmovap, 0x28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovntp, 0x2B, None, CpuAVX512F, Modrm|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovup, 0x10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovap, 0x28, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntp, 0x2B, CpuAVX512F, Modrm|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } +vmovup, 0x10, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +vmovd, 0x666E, CpuAVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovddup, 0xF212, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } +vmovddup, 0xF212, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } -vmovdqa64, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqa32, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovntdq, 0x66E7, None, CpuAVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovdqu32, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu64, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa64, 0x666F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa32, 0x666F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntdq, 0x66E7, CpuAVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } +vmovdqu32, 0xF36F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu64, 0xF36F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovhlps, 0x12, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovlhps, 0x16, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovhlps, 0x12, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovlhps, 0x16, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovhp, 0x16, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV||Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovhp, 0x17, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovlp, 0x12, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV||Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovlp, 0x13, None, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovhp, 0x16, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV||Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovhp, 0x17, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovlp, 0x12, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV||Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovlp, 0x13, CpuAVX512F, Modrm|EVexLIG|Space0F||Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovq, 0x666E, None, CpuAVX512F|Cpu64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } -vmovq, 0xF37E, None, CpuAVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovq, 0x66D6, None, CpuAVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vmovq, 0x666E, CpuAVX512F|Cpu64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } +vmovq, 0xF37E, CpuAVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovq, 0x66D6, CpuAVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vmovs, 0x10, None, , D|Modrm|EVexLIG|MaskingMorZ|||Disp8MemShift|NoSuf, { |Unspecified|BaseIndex, RegXMM } -vmovs, 0x10, None, , D|Modrm|EVexLIG|Masking=3||VexVVVV||NoSuf, { RegXMM, RegXMM, RegXMM } +vmovs, 0x10, , D|Modrm|EVexLIG|MaskingMorZ|||Disp8MemShift|NoSuf, { |Unspecified|BaseIndex, RegXMM } +vmovs, 0x10, , D|Modrm|EVexLIG|Masking=3||VexVVVV||NoSuf, { RegXMM, RegXMM, RegXMM } -vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovshdup, 0xF316, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovsldup, 0xF312, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpabs, 0x661e | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpand, 0x66db, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandn, 0x66df, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpor, 0x66eb, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub, 0x66fa | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxor, 0x66ef, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpabs, 0x661e | , CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpaddd, 0x66FE, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddq, 0x66d4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpand, 0x66db, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpandn, 0x66df, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuludq, 0x66f4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpor, 0x66eb, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66fa | , CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhdq, 0x666A, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhqdq, 0x666d, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckldq, 0x6662, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklqdq, 0x666c, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpxor, 0x66ef, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x661e, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x661e, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqd, 0x6676, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqq, 0x6629, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtd, 0x6666, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtq, 0x6637, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f/, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e/, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestm, 0x6627, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm, 0xf327, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm, 0x6627, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf327, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermd, 0x6636, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermps, 0x6616, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermilp, 0x6604 | , None, CpuAVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpermilp, 0x660C | , None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermilp, 0x6604 | , CpuAVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpermilp, 0x660C | , CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermpd, 0x6601, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermpd, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermq, 0x6600, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermq, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermpd, 0x6601, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermpd, 0x6616, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermq, 0x6600, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermq, 0x6636, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpmovdb, 0xF331, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovdb, 0xF331, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsdb, 0xF321, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusdb, 0xF311, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovdw, 0xF333, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovdw, 0xF333, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqb, 0xF332, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqb, 0xF332, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovqd, 0xF335, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqw, 0xF334, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovqw, 0xF334, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsqw, 0xF324, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusqw, 0xF314, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsxbd, 0x6621, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbd, 0x6631, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbd, 0x6621, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbd, 0x6631, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbq, 0x6622, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovzxbq, 0x6632, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovsxbq, 0x6622, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovzxbq, 0x6632, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovsxdq, 0x6625, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxdq, 0x6635, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxdq, 0x6625, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxdq, 0x6635, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwd, 0x6623, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwd, 0x6633, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwd, 0x6623, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwd, 0x6633, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwq, 0x6624, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwq, 0x6634, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vprol, 0x6672, 1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpror, 0x6672, 0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vprol, 0x6672/1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpror, 0x6672/0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufd, 0x6670, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsll, 0x66f2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsll, 0x6672 | , 6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsra, 0x66e2, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsra, 0x6672, 4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrl, 0x66d2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrl, 0x6672 | , 2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsll, 0x66f2 | , CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsll, 0x6672 | /6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsra, 0x66e2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsra, 0x6672/4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrl, 0x66d2 | , CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrl, 0x6672 | /2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14p, 0x664C, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14s, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp14p, 0x664C, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcp14s, 0x664D, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt14p, 0x664E, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrt14s, 0x664F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt14p, 0x664E, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrt14s, 0x664F, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vshuff32x4, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi32x4, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff32x4, 0x6623, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi32x4, 0x6643, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshuff64x2, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi64x2, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff64x2, 0x6623, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi64x2, 0x6643, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufp, 0xC6, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vshufp, 0xC6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpckhp, 0x15, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpcklp, 0x14, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpckhp, 0x15, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpcklp, 0x14, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512F instructions end. // AVX512CD instructions. -vpbroadcastmb2q, 0xF32A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpbroadcastmw2d, 0xF33A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpbroadcastmb2q, 0xF32A, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpbroadcastmw2d, 0xF33A, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpconflict, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpconflict, 0x66c4, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vplzcnt, 0x6644, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vplzcnt, 0x6644, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512CD instructions end. // AVX512ER instructions. -vexp2p, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vexp2p, 0x66C8, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrcp28p, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrcp28s, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp28p, 0x66CA, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vrcp28s, 0x66CB, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt28p, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrsqrt28s, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt28p, 0x66CC, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vrsqrt28s, 0x66CD, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512ER instructions end. // AVX512PF instructions. -vgatherpf0dpd, 0x66C6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vgatherpf0dps, 0x66C6, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vgatherpf0qp, 0x66C7, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } -vgatherpf1dpd, 0x66C6, 2, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vgatherpf1dps, 0x66C6, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vgatherpf1qp, 0x66C7, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } +vgatherpf0dpd, 0x66C6/1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf0dps, 0x66C6/1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf0qp, 0x66C7/1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } +vgatherpf1dpd, 0x66C6/2, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf1dps, 0x66C6/2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf1qp, 0x66C7/2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } -vscatterpf0dpd, 0x66C6, 5, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vscatterpf0dps, 0x66C6, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vscatterpf0qp, 0x66C7, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } -vscatterpf1dpd, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vscatterpf1dps, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vscatterpf1qp, 0x66C7, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } +vscatterpf0dpd, 0x66C6/5, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vscatterpf0dps, 0x66C6/5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vscatterpf0qp, 0x66C7/5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } +vscatterpf1dpd, 0x66C6/6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vscatterpf1dps, 0x66C6/6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vscatterpf1qp, 0x66C7/6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|BaseIndex } // AVX512PF instructions end. // CpuPREFETCHWT1 instructions. -prefetchwt1, 0x0F0D, 2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchwt1, 0x0F0D/2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CpuPREFETCHWT1 instructions end. // CLFLUSHOPT instructions. -clflushopt, 0x660fae, 7, CpuClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +clflushopt, 0x660fae/7, CpuClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLFLUSHOPT instructions end. // XSAVES/XRSTORS instructions. -xrstors, 0xfc7, 3, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xrstors64, 0xfc7, 3, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xsaves, 0xfc7, 5, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xsaves64, 0xfc7, 5, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xrstors, 0xfc7/3, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +xrstors64, 0xfc7/3, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsaves, 0xfc7/5, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +xsaves64, 0xfc7/5, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // XSAVES instructions end. // XSAVEC instructions. -xsavec, 0xfc7, 4, CpuXSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } -xsavec64, 0xfc7, 4, CpuXSAVEC|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsavec, 0xfc7/4, CpuXSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } +xsavec64, 0xfc7/4, CpuXSAVEC|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // XSAVEC instructions end. // SGX instructions. -encls, 0xf01cf, None, CpuSE1, NoSuf, {} -enclu, 0xf01d7, None, CpuSE1, NoSuf, {} -enclv, 0xf01c0, None, CpuSE1, NoSuf, {} +encls, 0xf01cf, CpuSE1, NoSuf, {} +enclu, 0xf01d7, CpuSE1, NoSuf, {} +enclv, 0xf01c0, CpuSE1, NoSuf, {} // SGX instructions end. // AVX512VL instructions. -vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } - -vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vpscatterq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } -vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vscatterqp, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } -vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } - -vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } - -vmovddup, 0xF212, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } - -vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } - -vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } - -vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } + +vpscatterdd, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vpscatterq, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } +vpscatterqd, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vscatterqp, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |Unspecified|BaseIndex } +vscatterqpd, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } + +vcvtdq2pd, 0xF3E6, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtdq2pd, 0xF3E6, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtudq2pd, 0xF37A, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtudq2pd, 0xF37A, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtph2ps, 0x6613, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2ps, 0x6613, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vcvtps2pd, 0x5A, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2pd, 0x5A, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtps2ph, 0x661D, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } + +vmovddup, 0xF212, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } + +vpmovdb, 0xF331, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovdb, 0xF331, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovdw, 0xF333, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovdw, 0xF333, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdw, 0xF323, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdw, 0xF313, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqb, 0xF332, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovqb, 0xF332, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovsqb, 0xF322, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovusqb, 0xF312, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } + +vpmovqd, 0xF335, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqd, 0xF335, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqd, 0xF325, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqd, 0xF315, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqw, 0xF334, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovqw, 0xF334, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovsxbd, 0x6621, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxbd, 0x6621, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxbd, 0x6631, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxbd, 0x6631, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } + +vpmovsxbq, 0x6622, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovsxbq, 0x6622, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vpmovzxbq, 0x6632, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovzxbq, 0x6632, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vpmovsxdq, 0x6625, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxdq, 0x6625, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxdq, 0x6635, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxdq, 0x6635, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwd, 0x6623, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxwd, 0x6623, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxwd, 0x6633, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxwd, 0x6633, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwq, 0x6624, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxwq, 0x6624, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxwq, 0x6634, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxwq, 0x6634, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } // AVX512VL instructions end. // AVX512BW instructions. -kadd, 0x4a, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kand, 0x41, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kandn, 0x42, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } -kmov, 0x90, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } -kmov, 0x91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, |Unspecified|BaseIndex } -kmov, 0xf292, None, CpuAVX512BW, D|Modrm|Vex128|Space0F||NoSuf, { , RegMask } -knot, 0x44, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -kor, 0x45, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kortest, 0x98, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -ktest, 0x99, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -kxnor, 0x46, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kxor, 0x47, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } -kunpckdq, 0x4B, None, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=2|NoSuf, { RegMask, RegMask, RegMask } -kunpckwd, 0x4B, None, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } -kshiftl, 0x6633, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } -kshiftr, 0x6631, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } - -vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vmovdqu8, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu16, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vpabs, 0x661c | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpmaxsb, 0x663C, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsb, 0x6638, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufb, 0x6600, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaddubsw, 0x6604, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminuw, 0x663A, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhrsw, 0x660B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpackssdw, 0x666B, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpacksswb, 0x6663, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackuswb, 0x6667, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackusdw, 0x662B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpadd, 0x66fc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpadds, 0x66ec | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddus, 0x66dc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpavg, 0x66e0 | (3 * ), None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxub, 0x66DE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminub, 0x66DA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub, 0x66f8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubs, 0x66e8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubus, 0x66d8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhbw, 0x6668, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklbw, 0x6660, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaxsw, 0x66EE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsw, 0x66EA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhuw, 0x66E4, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhw, 0x66E5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmullw, 0x66D5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllw, 0x6671, 6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsllw, 0x66F1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsraw, 0x6671, 4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsraw, 0x66E1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x6671, 2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x66D1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhwd, 0x6669, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklwd, 0x6661, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpalignr, 0x660F, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpblendm, 0x6666, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x6678 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x667a | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } - -vpermi2, 0x6675, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2, 0x667d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vperm, 0x668d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllvw, 0x6612, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsravw, 0x6611, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlvw, 0x6610, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpcmpeq, 0x6674 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgt, 0x6664 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x663f, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x663e, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x663f, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x663e, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } - -vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vpextrw, 0x66C5, None, CpuAVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr, 0x6614 | , None, CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr, 0x6614 | , None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } - -vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } - -vpmaddwd, 0x66F5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmov2m, 0xf329, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } -vpmovm2, 0xf328, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } - -vpmovswb, 0xF320, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovuswb, 0xF310, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovwb, 0xF330, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovsxbw, 0x6620, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpsadbw, 0x66F6, None, CpuAVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpshufhw, 0xF370, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshuflw, 0xF270, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vptestm, 0x6626, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm, 0xf326, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +kadd, 0x4a, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kand, 0x41, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kandn, 0x42, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kmov, 0x90, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x91, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0xf292, CpuAVX512BW, D|Modrm|Vex128|Space0F||NoSuf, { , RegMask } +knot, 0x44, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kor, 0x45, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kortest, 0x98, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +ktest, 0x99, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kxnor, 0x46, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kxor, 0x47, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kunpckdq, 0x4B, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=2|NoSuf, { RegMask, RegMask, RegMask } +kunpckwd, 0x4B, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } +kshiftl, 0x6633, CpuAVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } +kshiftr, 0x6631, CpuAVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } + +vdbpsadbw, 0x6642, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vmovdqu8, 0xF26F, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu16, 0xF26F, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vpabs, 0x661c | , CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpmaxsb, 0x663C, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsb, 0x6638, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshufb, 0x6600, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaddubsw, 0x6604, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxuw, 0x663E, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminuw, 0x663A, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhrsw, 0x660B, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpackssdw, 0x666B, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpacksswb, 0x6663, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackuswb, 0x6667, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackusdw, 0x662B, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpadd, 0x66fc | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpadds, 0x66ec | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddus, 0x66dc | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpavg, 0x66e0 | (3 * ), CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxub, 0x66DE, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminub, 0x66DA, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66f8 | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubs, 0x66e8 | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubus, 0x66d8 | , CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhbw, 0x6668, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklbw, 0x6660, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaxsw, 0x66EE, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsw, 0x66EA, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhuw, 0x66E4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhw, 0x66E5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullw, 0x66D5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllw, 0x6671/6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsllw, 0x66F1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsraw, 0x6671/4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsraw, 0x66E1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x6671/2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x66D1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhwd, 0x6669, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklwd, 0x6661, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpalignr, 0x660F, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpblendm, 0x6666, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x6678 | , CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x667a | , CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } + +vpermi2, 0x6675, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667d, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vperm, 0x668d, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllvw, 0x6612, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsravw, 0x6611, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlvw, 0x6610, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpcmpeq, 0x6674 | , CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgt, 0x6664 | , CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x663f, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x663e, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x663f/, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x663e/, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } + +vpslldq, 0x6673/7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrldq, 0x6673/3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vpextrw, 0x66C5, CpuAVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr, 0x6614 | , CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr, 0x6614 | , CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } + +vpinsrw, 0x66C4, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrw, 0x66C4, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsrb, 0x6620, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrb, 0x6620, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } + +vpmaddwd, 0x66F5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmov2m, 0xf329, CpuAVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } +vpmovm2, 0xf328, CpuAVX512BW, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } + +vpmovswb, 0xF320, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovswb, 0xF320, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovswb, 0xF320, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovuswb, 0xF310, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovuswb, 0xF310, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovuswb, 0xF310, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovwb, 0xF330, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovwb, 0xF330, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovwb, 0xF330, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovsxbw, 0x6620, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbw, 0x6620, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxbw, 0x6620, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxbw, 0x6630, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbw, 0x6630, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxbw, 0x6630, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpsadbw, 0x66F6, CpuAVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpshufhw, 0xF370, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshuflw, 0xF270, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vptestm, 0x6626, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf326, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512BW instructions end. @@ -2711,617 +2710,617 @@ vptestnm, 0xf326, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV| -kadd, 0x4A, None, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -ktest, 0x99, None, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } +kadd, 0x4A, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +ktest, 0x99, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } -vandnp, 0x55, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vandp, 0x54, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vorp, 0x56, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vxorp, 0x57, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vandnp, 0x55, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vandp, 0x54, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vorp, 0x56, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vxorp, 0x57, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vbroadcastf32x2, 0x6619, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcastf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti32x2, 0x6659, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcasti32x8, 0x665B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcastf32x2, 0x6619, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastf32x8, 0x661B, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti32x2, 0x6659, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcasti32x8, 0x665B, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcastf64x2, 0x661A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti64x2, 0x665A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastf64x2, 0x661A, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti64x2, 0x665A, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vcvtpd2qq, 0x667B, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2uqq, 0x6679, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtpd2qq, 0x667B, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtpd2uqq, 0x6679, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2qq, 0x667B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtps2qq, 0x667B, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2qq, 0x667B, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2qq, 0x667B, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtps2uqq, 0x6679, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2uqq, 0x6679, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2uqq, 0x6679, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtqq2pd, 0xF3E6, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtqq2pd, 0xF3E6, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuqq2pd, 0xF37A, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtqq2ps, 0x5b, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttpd2qq, 0x667A, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttpd2uqq, 0x6678, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2qq, 0x667A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2qq, 0x667A, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2qq, 0x667A, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2qq, 0x667A, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2uqq, 0x6678, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2uqq, 0x6678, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2uqq, 0x6678, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtuqq2ps, 0xf27a, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vextractf32x8, 0x661B, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti32x8, 0x663B, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vinsertf32x8, 0x661A, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti32x8, 0x663A, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vpextr, 0x6616, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } -vpinsr, 0x6622, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A|VexVVVV||Disp8MemShift|NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } +vpextr, 0x6616, CpuAVX512DQ|, Modrm|EVex128|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } +vpinsr, 0x6622, CpuAVX512DQ|, Modrm|EVex128|Space0F3A|VexVVVV||Disp8MemShift|NoSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } -vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vextractf64x2, 0x6619, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti64x2, 0x6639, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vinsertf64x2, 0x6618, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti64x2, 0x6638, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } -vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } -vfpclasspz, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask } -vfpclasspx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } -vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM||Unspecified|BaseIndex, RegMask } -vfpclasss, 0x67, None, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } +vfpclassp, 0x6666, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } +vfpclassp, 0x6666, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } +vfpclasspz, 0x6666, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask } +vfpclasspx, 0x6666, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } +vfpclasspy, 0x6666, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM||Unspecified|BaseIndex, RegMask } +vfpclasss, 0x67, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } -vpmov2m, 0xf339, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } -vpmovm2, 0xf338, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpmov2m, 0xf339, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } +vpmovm2, 0xf338, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullq, 0x6640, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vrangep, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vranges, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrangep, 0x6650, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vranges, 0x6651, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vreducep, 0x56, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vreduces, 0x57, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vreducep, 0x56, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vreduces, 0x57, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512DQ instructions end. // CLWB instructions. -clwb, 0x660fae, 6, CpuCLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +clwb, 0x660fae/6, CpuCLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLWB instructions end. // AVX512IFMA instructions -vpmadd52huq, 0x66B5, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52huq, 0x66B5, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52luq, 0x66B4, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512IFMA instructions end // AVX-IFMA instructions. -vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52huq, 0x66B5, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52luq, 0x66B4, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // AVX-IFMA instructions end. // AVX512VBMI instructions -vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmultishiftqb, 0x6683, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512VBMI instructions end // AVX512_4FMAPS instructions -v4fmaddps, 0xf29a, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fnmaddps, 0xf2aa, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fmaddss, 0xf29b, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } -v4fnmaddss, 0xf2ab, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fmaddps, 0xf29a, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fnmaddps, 0xf2aa, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fmaddss, 0xf29b, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fnmaddss, 0xf2ab, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512_4FMAPS instructions end // AVX512_4VNNIW instructions -vp4dpwssd, 0xf252, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -vp4dpwssds, 0xf253, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssd, 0xf252, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssds, 0xf253, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } // AVX512_4VNNIW instructions end // AVX512_VPOPCNTDQ instructions -vpopcnt, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt, 0x6655, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512_VPOPCNTDQ instructions end // AVX512_VBMI2 instructions -vpcompressb, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressw, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressb, 0x6663, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressw, 0x6663, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandb, 0x6662, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandw, 0x6662, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshldv, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldv, 0x6671, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldvw, 0x6670, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdv, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdv, 0x6673, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdvw, 0x6672, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshld, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshld, 0x6671, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldw, 0x6670, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrd, 0x6673, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdw, 0x6672, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VBMI2 instructions end // AVX512_VNNI instructions -vpdpbusd, 0x6650, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssd, 0x6652, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusd, 0x6650, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssd, 0x6652, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpbusds, 0x6651, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssds, 0x6653, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusds, 0x6651, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssds, 0x6653, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VNNI instructions end // AVX_VNNI instructions -vpdpbusd, 0x6650, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssd, 0x6652, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusd, 0x6650, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssd, 0x6652, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbusds, 0x6651, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusds, 0x6651, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssds, 0x6653, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX_VNNI instructions end // AVX-VNNI-INT8 instructions. -vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbuud, 0x50, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbuuds, 0x51, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssd, 0xf250, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssds, 0xf251, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsud, 0xf350, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsuds, 0xf351, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // AVX-VNNI-INT8 instructions end. // AVX512_BITALG instructions -vpopcnt, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt, 0x6654, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38||Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufbitqmb, 0x668f, None, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpshufbitqmb, 0x668f, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512_BITALG instructions end // AVX512 + GFNI instructions -vgf2p8affineinvqb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8affineqb, 0x66ce, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8mulb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineinvqb, 0x66cf, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineqb, 0x66ce, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8mulb, 0x66cf, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + GFNI instructions end // AVX512 + VAES instructions -vaesdec, 0x66de, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesdeclast, 0x66df, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesenc, 0x66dc, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesenclast, 0x66dd, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesdec, 0x66de, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesdeclast, 0x66df, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesenc, 0x66dc, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesenclast, 0x66dd, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + VAES instructions end // AVX512 + VPCLMULQDQ instructions -vpclmulqdq, 0x6644, None, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmullqlqdq, 0x6644, 0x00, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmulhqlqdq, 0x6644, 0x01, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmullqhqdq, 0x6644, 0x10, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulqdq, 0x6644, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmullqlqdq, 0x6644/0x00, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulhqlqdq, 0x6644/0x01, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmullqhqdq, 0x6644/0x10, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulhqhqdq, 0x6644/0x11, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + VPCLMULQDQ instructions end // INVLPGB instructions -invlpgb, 0xf01fe, None, CpuINVLPGB, NoSuf, {} -invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +invlpgb, 0xf01fe, CpuINVLPGB, NoSuf, {} +invlpgb, 0xf01fe, CpuINVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // INVLPGB instructions end // TLBSYNC instructions -tlbsync, 0xf01ff, None, CpuTLBSYNC, NoSuf, {} +tlbsync, 0xf01ff, CpuTLBSYNC, NoSuf, {} // TLBSYNC instructions end // CLZERO instructions -clzero, 0xf01fc, None, CpuCLZERO, NoSuf, {} -clzero, 0xf01fc, None, CpuCLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +clzero, 0xf01fc, CpuCLZERO, NoSuf, {} +clzero, 0xf01fc, CpuCLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } // CLZERO instructions end // MONITORX/MWAITX instructions -monitorx, 0xf01fa, None, CpuMWAITX, NoSuf, {} -monitorx, 0xf01fa, None, CpuMWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +monitorx, 0xf01fa, CpuMWAITX, NoSuf, {} +monitorx, 0xf01fa, CpuMWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // The 64-bit form exists only for compatibility with older gas. -monitorx, 0xf01fa, None, CpuMWAITX|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +monitorx, 0xf01fa, CpuMWAITX|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } -mwaitx, 0xf01fb, None, CpuMWAITX, NoSuf, {} +mwaitx, 0xf01fb, CpuMWAITX, NoSuf, {} // The 64-bit form exists only for compatibility with older gas. -mwaitx, 0xf01fb, None, CpuMWAITX, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } +mwaitx, 0xf01fb, CpuMWAITX, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } // MONITORX/MWAITX instructions end // OSPKE instructions. -rdpkru, 0xf01ee, None, CpuOSPKE, NoSuf, {} -wrpkru, 0xf01ef, None, CpuOSPKE, NoSuf, {} +rdpkru, 0xf01ee, CpuOSPKE, NoSuf, {} +wrpkru, 0xf01ef, CpuOSPKE, NoSuf, {} // OSPKE instructions end. // RDPID instructions. -rdpid, 0xf30fc7, 7, CpuRDPID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Reg32 } -rdpid, 0xf30fc7, 7, CpuRDPID|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } +rdpid, 0xf30fc7/7, CpuRDPID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Reg32 } +rdpid, 0xf30fc7/7, CpuRDPID|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } // RDPID instructions end. // PTWRITE instructions. -ptwrite, 0xf30fae, 4, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Unspecified|BaseIndex } -ptwrite, 0xf30fae, 4, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } +ptwrite, 0xf30fae/4, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Unspecified|BaseIndex } +ptwrite, 0xf30fae/4, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } // PTWRITE instructions end. // CET instructions. -incsspd, 0xf30fae, 5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } -incsspq, 0xf30fae, 5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } -rdsspd, 0xf30f1e, 1, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } -rdsspq, 0xf30f1e, 1, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } -saveprevssp, 0xf30f01ea, None, CpuSHSTK, NoSuf, {} -rstorssp, 0xf30f01, 5, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -wrssd, 0x0f38f6, None, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } -wrssq, 0x0f38f6, None, CpuSHSTK|Cpu64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } -wrussd, 0x660f38f5, None, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } -wrussq, 0x660f38f5, None, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } -setssbsy, 0xf30f01e8, None, CpuSHSTK, NoSuf, {} -clrssbsy, 0xf30fae, 6, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -endbr64, 0xf30f1efa, None, CpuIBT, NoSuf, {} -endbr32, 0xf30f1efb, None, CpuIBT, NoSuf, {} +incsspd, 0xf30fae/5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +incsspq, 0xf30fae/5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } +rdsspd, 0xf30f1e/1, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +rdsspq, 0xf30f1e/1, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } +saveprevssp, 0xf30f01ea, CpuSHSTK, NoSuf, {} +rstorssp, 0xf30f01/5, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +wrssd, 0x0f38f6, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrssq, 0x0f38f6, CpuSHSTK|Cpu64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } +wrussd, 0x660f38f5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrussq, 0x660f38f5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } +setssbsy, 0xf30f01e8, CpuSHSTK, NoSuf, {} +clrssbsy, 0xf30fae/6, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +endbr64, 0xf30f1efa, CpuIBT, NoSuf, {} +endbr32, 0xf30f1efb, CpuIBT, NoSuf, {} // notrack prefix -notrack, 0x3e, None, CpuIBT, NoSuf|IsPrefix, {} +notrack, 0x3e, CpuIBT, NoSuf|IsPrefix, {} // CET instructions end. // WBNOINVD instruction. -wbnoinvd, 0xf30f09, None, CpuWBNOINVD, NoSuf, {} +wbnoinvd, 0xf30f09, CpuWBNOINVD, NoSuf, {} // WBNOINVD instruction end. // PCONFIG instruction. -pconfig, 0x0f01c5, None, CpuPCONFIG, NoSuf, {} +pconfig, 0x0f01c5, CpuPCONFIG, NoSuf, {} // PCONFIG instruction end. // WAITPKG instructions. -umonitor, 0xf30fae, 6, CpuWAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } -tpause, 0x660fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } -tpause, 0x660fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } -umwait, 0xf20fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } -umwait, 0xf20fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } +umonitor, 0xf30fae/6, CpuWAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } +tpause, 0x660fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } +tpause, 0x660fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } +umwait, 0xf20fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } +umwait, 0xf20fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } // WAITPKG instructions end. // CLDEMOTE instructions. -cldemote, 0x0f1c, 0, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +cldemote, 0x0f1c/0, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLDEMOTE instructions end. // MOVDIR[I,64B] instructions. -movdiri, 0xf38f9, None, CpuMOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movdiri, 0xf38f9, CpuMOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +movdir64b, 0x660f38f8, CpuMOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // MOVEDIR instructions end. // AVX512_BF16 instructions. -vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vcvtne2ps2bf16, 0xf272, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, Modrm|Space0F38||Masking=3|VexW0|Broadcast|NoSuf, { |Dword, } +vcvtneps2bf16, 0xf372, CpuAVX512_BF16|, Modrm|Space0F38||Masking=3|VexW0|Broadcast|NoSuf, { |Dword, } -vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdpbf16ps, 0xf352, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_BF16 instructions end. // AVX-NE-CONVERT instructions. -vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } -vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneps2bf16, 0xf372, None, CpuAVX_NE_CONVERT, Modrm||Space0F38|VexW0|NoSuf|, { , RegXMM } +vbcstnebf162ps, 0xf3b1, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } +vbcstnesh2ps, 0x66b1, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneebf162ps, 0xf3b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneeph2ps, 0x66b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneobf162ps, 0xf2b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneoph2ps, 0xb0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneps2bf16, 0xf372, CpuAVX_NE_CONVERT, Modrm||Space0F38|VexW0|NoSuf|, { , RegXMM } // AVX-NE-CONVERT instructions end. // ENQCMD instructions. -enqcmd, 0xf20f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -enqcmds, 0xf30f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmd, 0xf20f38f8, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmds, 0xf30f38f8, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // ENQCMD instructions end. // VP2INTERSECT instructions. -vp2intersect, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vp2intersect, 0xf268, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // VP2INTERSECT instructions end. // MCOMMIT instruction -mcommit, 0xf30f01fa, None, CpuMCOMMIT, NoSuf, {} +mcommit, 0xf30f01fa, CpuMCOMMIT, NoSuf, {} // MCOMMIT instruction end // SNP instructions -psmash, 0xf30f01ff, None, CpuSNP|Cpu64, NoSuf, {} -psmash, 0xf30f01ff, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } -pvalidate, 0xf20f01ff, None, CpuSNP, NoSuf, {} -pvalidate, 0xf20f01ff, None, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } -rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, NoSuf, {} -rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } -rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, NoSuf, {} -rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +psmash, 0xf30f01ff, CpuSNP|Cpu64, NoSuf, {} +psmash, 0xf30f01ff, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +pvalidate, 0xf20f01ff, CpuSNP, NoSuf, {} +pvalidate, 0xf20f01ff, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, NoSuf, {} +rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } +rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, NoSuf, {} +rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } // The single-operand forms exist only for compatibility with older gas. -pvalidate, 0xf20f01ff, None, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } -rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +pvalidate, 0xf20f01ff, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } // SNP instructions end // RMPQUERY instruction -rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, NoSuf, {} -rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +rmpquery, 0xf30f01fd, CpuRMPQUERY|Cpu64, NoSuf, {} +rmpquery, 0xf30f01fd, CpuRMPQUERY|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } // RMPQUERY instruction end // RDPRU instruction -rdpru, 0x0f01fd, None, CpuRDPRU, NoSuf, {} +rdpru, 0x0f01fd, CpuRDPRU, NoSuf, {} // RDPRU instruction end // SERIALIZE instruction. -serialize, 0x0f01e8, None, CpuSERIALIZE, NoSuf, {} +serialize, 0x0f01e8, CpuSERIALIZE, NoSuf, {} // SERIALIZE instruction end. // TSXLDTRK instructions. -xsusldtrk, 0xf20f01e8, None, CpuTSXLDTRK, NoSuf, {} -xresldtrk, 0xf20f01e9, None, CpuTSXLDTRK, NoSuf, {} +xsusldtrk, 0xf20f01e8, CpuTSXLDTRK, NoSuf, {} +xresldtrk, 0xf20f01e9, CpuTSXLDTRK, NoSuf, {} // TSXLDTRK instructions end. // AMX instructions. -ldtilecfg, 0x49, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } -sttilecfg, 0x6649, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +ldtilecfg, 0x49, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +sttilecfg, 0x6649, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } -tdpbf16ps, 0xf35c, None, CpuAMX_BF16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpfp16ps, 0xf25c, None, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbssd, 0xf25e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbuud, 0x5e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbusd, 0x665e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbsud, 0xf35e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbf16ps, 0xf35c, CpuAMX_BF16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpfp16ps, 0xf25c, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbssd, 0xf25e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbuud, 0x5e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbusd, 0x665e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbsud, 0xf35e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tileloadd, 0xf24b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } -tileloaddt1, 0x664b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } -tilestored, 0xf34b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } +tileloadd, 0xf24b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloaddt1, 0x664b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tilestored, 0xf34b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } -tilerelease, 0x49c0, None, CpuAMX_TILE|Cpu64, Vex128|Space0F38|VexW0|NoSuf, {} +tilerelease, 0x49c0, CpuAMX_TILE|Cpu64, Vex128|Space0F38|VexW0|NoSuf, {} -tilezero, 0xf249, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } +tilezero, 0xf249, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } // AMX instructions end. // KEYLOCKER instructions. -loadiwkey, 0xf30f38dc, None, CpuKL, Load|Modrm|NoSuf, { RegXMM, RegXMM } -encodekey128, 0xf30f38fa, None, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } -encodekey256, 0xf30f38fb, None, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } -aesenc128kl, 0xf30f38dc, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesdec128kl, 0xf30f38dd, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesenc256kl, 0xf30f38de, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesdec256kl, 0xf30f38df, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesencwide128kl, 0xf30f38d8, 0, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesdecwide128kl, 0xf30f38d8, 1, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesencwide256kl, 0xf30f38d8, 2, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesdecwide256kl, 0xf30f38d8, 3, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +loadiwkey, 0xf30f38dc, CpuKL, Load|Modrm|NoSuf, { RegXMM, RegXMM } +encodekey128, 0xf30f38fa, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey256, 0xf30f38fb, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } +aesenc128kl, 0xf30f38dc, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec128kl, 0xf30f38dd, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc256kl, 0xf30f38de, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec256kl, 0xf30f38df, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesencwide128kl, 0xf30f38d8/0, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide128kl, 0xf30f38d8/1, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide256kl, 0xf30f38d8/2, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide256kl, 0xf30f38d8/3, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } // KEYLOCKER instructions end. // TDX instructions. -tdcall, 0x660f01cc, None, CpuTDX, NoSuf, {} -seamret, 0x660f01cd, None, CpuTDX|Cpu64, NoSuf, {} -seamops, 0x660f01ce, None, CpuTDX|Cpu64, NoSuf, {} -seamcall, 0x660f01cf, None, CpuTDX|Cpu64, NoSuf, {} +tdcall, 0x660f01cc, CpuTDX, NoSuf, {} +seamret, 0x660f01cd, CpuTDX|Cpu64, NoSuf, {} +seamops, 0x660f01ce, CpuTDX|Cpu64, NoSuf, {} +seamcall, 0x660f01cf, CpuTDX|Cpu64, NoSuf, {} // TDX instructions end. // UINTR instructions. -uiret, 0xf30f01ec, None, CpuUINTR|Cpu64, NoSuf, {} -clui, 0xf30f01ee, None, CpuUINTR|Cpu64, NoSuf, {} -stui, 0xf30f01ef, None, CpuUINTR|Cpu64, NoSuf, {} -testui, 0xf30f01ed, None, CpuUINTR|Cpu64, NoSuf, {} -senduipi, 0xf30fc7, 6, CpuUINTR|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } +uiret, 0xf30f01ec, CpuUINTR|Cpu64, NoSuf, {} +clui, 0xf30f01ee, CpuUINTR|Cpu64, NoSuf, {} +stui, 0xf30f01ef, CpuUINTR|Cpu64, NoSuf, {} +testui, 0xf30f01ed, CpuUINTR|Cpu64, NoSuf, {} +senduipi, 0xf30fc7/6, CpuUINTR|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } // UINTR instructions end. // HRESET instructions. -hreset, 0xf30f3af0c0, None, CpuHRESET, NoSuf, { Imm8 } +hreset, 0xf30f3af0c0, CpuHRESET, NoSuf, { Imm8 } // HRESET instructions end. // FP16 (HFNI) instructions. -vfcmaddcph, 0xf256, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmaddcsh, 0xf257, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmaddcph, 0xf256, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmaddcsh, 0xf257, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddcph, 0xf356, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddcsh, 0xf357, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddcph, 0xf356, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmaddcsh, 0xf357, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfcmulcph, 0xf2d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmulcph, 0xf2d6, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmulcsh, 0xf2d7, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmulcph, 0xf3d6, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmulcsh, 0xf3d7, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmpph, 0xc2, 0x, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpph, 0xc2/0x, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpph, 0xc2, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpsh, 0xf3c2/0x, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpsh, 0xf3c2, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtdq2ph, 0x5b, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtudq2ph, 0xf27a, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtqq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtqq2ph, 0x5b, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtuqq2ph, 0xf27a, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtpd2ph, 0x665a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } +vcvtpd2ph, 0x665a, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|NoSuf||, { |Qword, RegXMM } -vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } +vcvtps2phx, 0x661d, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|, { |Dword, } -vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtw2ph, 0xf37d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuw2ph, 0xf27d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2dq, 0x665b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2dq, 0x665b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2dq, 0x665b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2udq, 0x79, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2udq, 0x79, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2udq, 0x79, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2qq, 0x667b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2qq, 0x667b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2qq, 0x667b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2uqq, 0x6679, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2uqq, 0x6679, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2uqq, 0x6679, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2pd, 0x5a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2pd, 0x5a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2pd, 0x5a, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2w, 0x667d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2uw, 0x7d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2w, 0x667d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2uw, 0x7d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtsd2sh, 0xf25a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sh, 0x1d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2sh, 0xf25a, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sh, 0x1d, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2sd, 0xf35a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2ss, 0x13, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2sd, 0xf35a, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2ss, 0x13, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2si, 0xf32d, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvtsh2si, 0xf32d, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2dq, 0xf35b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2dq, 0xf35b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2dq, 0xf35b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2udq, 0x78, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2udq, 0x78, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2udq, 0x78, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2udq, 0x78, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2qq, 0x667a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2qq, 0x667a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2qq, 0x667a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2qq, 0x667a, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2uqq, 0x6678, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2uqq, 0x6678, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2uqq, 0x6678, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2psx, 0x6613, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2psx, 0x6613, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2psx, 0x6613, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2psx, 0x6613, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2w, 0x667c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2uw, 0x7c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2w, 0x667c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2uw, 0x7c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvttsh2si, 0xf32c, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vfpclassph, 0x66, None, CpuAVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8, |Word, RegMask } +vfpclassph, 0x66, CpuAVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8, |Word, RegMask } -vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } -vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } +vmovw, 0x666e, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } +vmovw, 0x667e, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } -vrcpph, 0x664c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcpph, 0x664c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcpsh, 0x664d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrcpsh, 0x664d, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrtph, 0x664e, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrtsh, 0x664f, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } // FP16 (HFNI) instructions end. // PREFETCHI instructions. -prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchit0, 0xf18/7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchit1, 0xf18/6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // PREFETCHI instructions end. // CMPCCXADD instructions. -cmpxadd, 0x66e, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +cmpxadd, 0x66e, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. // WRMSRNS instruction. -wrmsrns, 0x0f01c6, None, CpuWRMSRNS, NoSuf, {} +wrmsrns, 0x0f01c6, CpuWRMSRNS, NoSuf, {} // WRMSRNS instruction end. // MSRLIST instructions. -rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, NoSuf, {} -wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, NoSuf, {} +rdmsrlist, 0xf20f01c6, CpuMSRLIST|Cpu64, NoSuf, {} +wrmsrlist, 0xf30f01c6, CpuMSRLIST|Cpu64, NoSuf, {} // MSRLIST instructions end. // RAO-INT instructions. -aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aadd, 0xf38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aand, 0x660f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aor, 0xf20f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +axor, 0xf30f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // RAO-INT instructions end. diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 4257cc8a3de..6f6e1a68bbb 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -58995,7 +58995,7 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "prefetchit0", 0x18, 1, 0x7, + { "prefetchit0", 0x18, 1, 7, { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -59008,7 +59008,7 @@ static const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "prefetchit1", 0x18, 1, 0x6, + { "prefetchit1", 0x18, 1, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },