From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 21 Aug 2006 17:20:35 +0000 (-0400)
Subject: Merge zizzer:/z/m5/Bitkeeper/newmem
X-Git-Tag: m5_2.0_beta1_patch1~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=689eb39d4862df05dacb5030494000230dcfb5a7;p=gem5.git

Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

src/python/m5/objects/BaseCPU.py:
    Merge duplicate change

--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
---

689eb39d4862df05dacb5030494000230dcfb5a7
diff --cc tests/configs/simple-timing.py
index 9a5b20e88,78dfabe3b..7bb76db0e
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@@ -40,7 -40,6 +40,7 @@@ cpu = TimingSimpleCPU(
  cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                                MyCache(size = '2MB'))
  cpu.mem = cpu.dcache
- 
++cpu.mem = cpu.dcache
  system = System(cpu = cpu,
                  physmem = PhysicalMemory(),
                  membus = Bus())