From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 9 Jul 2019 10:14:50 +0000 (+0200)
Subject: soc_sdram: limit main_ram to 512MB for now
X-Git-Tag: 24jan2021_ls180~1113
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68a503174;p=litex.git

soc_sdram: limit main_ram to 512MB for now

Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 27e6f324..1706ae41 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -69,6 +69,7 @@ class SoCSDRAM(SoCCore):
         main_ram_size = 2**(geom_settings.bankbits +
                             geom_settings.rowbits +
                             geom_settings.colbits)*phy.settings.databits//8
+        main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
         self.config["L2_SIZE"] = self.l2_size
 
         # add a Wishbone interface to the DRAM