From: Paul Sajna Date: Sun, 1 Mar 2020 09:39:03 +0000 (-0800) Subject: add riscv-sifive-elf triple X-Git-Tag: 24jan2021_ls180~609^2^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68c013d13fc2c77ab7c64a0269caa5d7004667fb;p=litex.git add riscv-sifive-elf triple --- diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index dfb790c0..b58ac1a1 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -48,7 +48,7 @@ class BlackParrotRV64(CPU): name = "blackparrot" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf") linker_output_format = "elf64-littleriscv" io_regions = {0x30000000: 0x20000000} # origin, length diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 9bc97089..2c3d967c 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -18,7 +18,7 @@ class Minerva(CPU): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux") + "riscv64-linux", "riscv-sifive-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index c2122677..0729af1c 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -35,7 +35,7 @@ class PicoRV32(CPU): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux") + "riscv64-linux", "riscv-sifive-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 108a4967..3f94cf2d 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -67,7 +67,7 @@ class RocketRV64(CPU): name = "rocket" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf") linker_output_format = "elf64-littleriscv" io_regions = {0x10000000: 0x70000000} # origin, length diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 08c2c8a2..996cbf76 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -79,7 +79,7 @@ class VexRiscv(CPU, AutoCSR): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux") + "riscv64-linux", "riscv-sifive-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length