From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 15 May 2012 13:18:03 +0000 (+0200)
Subject: bus/wishbone2asmi: fix cache tag size
X-Git-Tag: 24jan2021_ls180~2099^2~946
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68cd445662c8d015ff4ec9a65e8e68e3427d366d;p=litex.git

bus/wishbone2asmi: fix cache tag size
---

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
index 856be225..5cfe92d5 100644
--- a/migen/bus/wishbone2asmi.py
+++ b/migen/bus/wishbone2asmi.py
@@ -29,7 +29,7 @@ class WB2ASMI:
 		offsetbits = log2_int(adw//32)
 		addressbits = aaw + offsetbits
 		linebits = log2_int(self.cachesize) - offsetbits
-		tagbits = aaw - linebits
+		tagbits = addressbits - linebits
 		adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
 		
 		# Data memory
@@ -63,7 +63,7 @@ class WB2ASMI:
 		]
 		
 		# Tag memory
-		tag_layout = [("tag", BV(linebits)), ("dirty", BV(1))]
+		tag_layout = [("tag", BV(tagbits)), ("dirty", BV(1))]
 		tag_do = Record(tag_layout)
 		tag_do_raw = tag_do.to_signal(comb, False)
 		tag_di = Record(tag_layout)