From: lkcl <lkcl@web>
Date: Tue, 17 May 2022 17:17:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2178
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68d06d736f8ca8bc49f8aa8877b49e286444d0fc;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index db2c0aa65..27a24a641 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -90,9 +90,11 @@ OPF ISA WG):
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
 |19 |RT   |  |mask |BFA  |     |XO[0:4]|XO[5:9]|/ |          |
 |19 |     |  |     |     |     |1 //// |00011  |  |rsvd      |
-|19 |RT   |M |mask |BFA  | 0 0 |0 mode |00011  |Rc|crrweird  |
-|19 |RA   |M |mask |BF   | 0 1 |0 mode |00011  |/ |mtcrweird |
-|19 |BT   |M |mask |BFA  | 1 0 |0 mode |00011  |/ |crweirder |
+|19 |RT   |M |mask |BFA  | 0 0 |0 mode |00011  |0 |crrweird  |
+|19 |RT   |0 |mask |BFA  | 0 0 |0 mode |00011  |1 |mfcrweird |
+|19 |RA   |1 |mask |BF   | 0 0 |0 mode |00011  |1 |mtcrrweird |
+|19 |RA   |M |mask |BF   | 0 1 |0 mode |00011  |0 |mtcrweird |
+|19 |BT   |M |mask |BFA  | 0 1 |0 mode |00011  |1 |crweirder |
 |19 |BF //|M |mask |BFA  | 1 1 |0 mode |00011  |0 |crweird   |
 |19 |BF //|M |mask |BFA  | 1 1 |0 mode |00011  |1 |mcrfm     |
 
@@ -111,11 +113,50 @@ bit 19=0, bit 20=0
     n3 = mask[3] & (mode[3] == creg[3])
     result = n0|n1|n2|n3 if M else n0&n1&n2&n3
     RT[63] = result # MSB0 numbering, 63 is LSB
-    If Rc:
-        CR0 = analyse(RT)
 
 When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
-SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
+SVP64 type operation and as such can use RC1 Data-dependent
+Mode capability
+
+**mfcrrweird**
+
+mode is encoded in XO and is 4 bits
+
+bit 19=0, bit 20=0
+
+    mfcrrweird: RT, BFA, mask.mode
+
+    creg = CR{BFA}
+    n0 = mask[0] & (mode[0] == creg[0])
+    n1 = mask[1] & (mode[1] == creg[1])
+    n2 = mask[2] & (mode[2] == creg[2])
+    n3 = mask[3] & (mode[3] == creg[3])
+    result = n0||n1||n2||n3
+    RT[60:63] = result # MSB0 numbering, 63 is LSB
+
+When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
+SVP64 type operation and as such can use RC1 Data-dependent
+Mode capability
+
+**mtcrrweird**
+
+mode is encoded in XO and is 4 bits
+
+bit 19=0, bit 20=0
+
+    mtcrrweird: BF, RA, M, mask.mode
+
+    n0 = mask[0] & (mode[0] == RA[63])
+    n1 = mask[1] & (mode[1] == RA[62])
+    n2 = mask[2] & (mode[2] == RA[61])
+    n3 = mask[3] & (mode[3] == RA[60])
+    result = n0 || n1 || n2 || n3
+    if M:
+        result |= CR{BF} & ~mask
+    CR{BF} = result
+
+When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
+SVP64 type operation and as such can use RC1 Data-dependent
 Mode capability
 
 **mtcrweird**