From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 10 Mar 2006 21:26:31 +0000 (-0500)
Subject: Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
X-Git-Tag: m5_2.0_beta1~204
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68d7382cf37a3f765a7cc650fcef04fb1548fa39;p=gem5.git

Eliminated TARGET_ALPHA, since THE_ISA provides the same function.

--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
---

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 878193881..d09b39a09 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -43,8 +43,6 @@ class FastCPU;
 class FullCPU;
 class Checkpoint;
 
-#define TARGET_ALPHA
-
 class StaticInst;
 class StaticInstPtr;
 
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 6f725d1e4..6cc586467 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -284,7 +284,7 @@ class CPUExecContext
     template <class T>
     Fault read(CpuRequestPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@@ -300,7 +300,7 @@ class CPUExecContext
     template <class T>
     Fault write(CpuRequestPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 0352e9972..8e1e0f42a 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -208,7 +208,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@@ -230,7 +230,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 4ac8c845c..3fa84d499 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -941,9 +941,9 @@ SimpleCPU::tick()
 
     // maintain $r0 semantics
     cpuXC->setIntReg(ZeroReg, 0);
-#ifdef TARGET_ALPHA
+#if THE_ISA == ALPHA_ISA
     cpuXC->setFloatRegDouble(ZeroReg, 0.0);
-#endif // TARGET_ALPHA
+#endif // ALPHA_ISA
 
     if (status() == IcacheAccessComplete) {
         // We've already fetched an instruction and were stalled on an