From: Arnaud Durand <arnaud.durand@unifr.ch>
Date: Wed, 3 Jul 2019 22:58:26 +0000 (+0200)
Subject: Add verilog submodule from CPU cores to manifest
X-Git-Tag: 24jan2021_ls180~1130^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68eeba918186f5bd3d3f4e0552b286f7db08d5a3;p=litex.git

Add verilog submodule from CPU cores to manifest
---

diff --git a/MANIFEST.in b/MANIFEST.in
index 26d68170..a15c845d 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,5 +1,8 @@
 graft litex/build/sim
 graft litex/soc/software
 graft litex/soc/cores/cpu/lm32/verilog
+graft litex/soc/cores/cpu/minerva/verilog
 graft litex/soc/cores/cpu/mor1kx/verilog
-graft litex/soc/cores/cpu/picorv32/verilog
\ No newline at end of file
+graft litex/soc/cores/cpu/picorv32/verilog
+graft litex/soc/cores/cpu/rocket/verilog
+graft litex/soc/cores/cpu/vexriscv/verilog