From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 23 Apr 2019 11:17:54 +0000 (+0200)
Subject: soc/integration: also add sha-1/date to generated software files
X-Git-Tag: 24jan2021_ls180~1283
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68f12495cfb974d83557cd5a4bcc89ed2fde1c2e;p=litex.git

soc/integration: also add sha-1/date to generated software files
---

diff --git a/litex/build/tools.py b/litex/build/tools.py
index d0d90c7f..7800fc22 100644
--- a/litex/build/tools.py
+++ b/litex/build/tools.py
@@ -5,6 +5,8 @@ import re
 import subprocess
 import sys
 import ctypes
+import time
+import datetime
 
 
 def language_by_filename(name):
@@ -91,3 +93,11 @@ else:
 
 def git_revision():
     return subprocess.check_output(["git", "rev-parse", "--short", "HEAD"]).strip().decode("utf-8")
+
+def generated_banner(line_comment="//"):
+    r = line_comment + "-"*60 + "\n"
+    r += line_comment + " Generated by Migen & LiteX / "
+    r += git_revision() + " / "
+    r += "{}\n".format(datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S"))
+    r += line_comment + "-"*60 + "\n"
+    return r
\ No newline at end of file
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 6ab317a7..0f70e662 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -1,8 +1,6 @@
 from functools import partial
 from operator import itemgetter
 import collections
-import time
-import datetime
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
@@ -10,7 +8,7 @@ from migen.fhdl.tools import *
 from migen.fhdl.namer import build_namespace
 from migen.fhdl.conv_output import ConvOutput
 
-from litex.build.tools import git_revision
+from litex.build.tools import generated_banner
 
 
 _reserved_keywords = {
@@ -406,12 +404,7 @@ def convert(f, ios=None, name="top",
     ns.clock_domains = f.clock_domains
     r.ns = ns
 
-    src = "//" + "-"*60 + "\n"
-    src +=  "// Generated by Migen & LiteX / ".format(git_revision())
-    src += git_revision() + " / "
-    src += "{}\n".format(datetime.datetime.fromtimestamp(
-                time.time()).strftime("%Y-%m-%d %H:%M:%S"))
-    src += "//" + "-"*60 + "\n"
+    src = generated_banner("//")
     src += _printheader(f, ios, name, ns, attr_translate,
                         reg_initialization=reg_initialization)
     if regular_comb:
diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index 49acb5aa..99b56977 100644
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -5,6 +5,8 @@ from migen import *
 
 from litex.soc.interconnect.csr import CSRStatus
 
+from litex.build.tools import generated_banner
+
 def get_cpu_mak(cpu):
     # select between clang and gcc
     clang = os.getenv("CLANG", "")
@@ -69,6 +71,7 @@ def get_linker_regions(regions):
 
 
 def get_mem_header(regions, flash_boot_address):
+    r = generated_banner("//")
     r = "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
     for name, base, size in regions:
         r += "#define {name}_BASE 0x{base:08x}\n#define {name}_SIZE 0x{size:08x}\n\n".format(name=name.upper(), base=base, size=size)
@@ -120,7 +123,8 @@ def _get_rw_functions_c(reg_name, reg_base, nwords, busword, read_only, with_acc
 
 
 def get_csr_header(regions, constants, with_access_functions=True, with_shadow_base=True, shadow_base=0x80000000):
-    r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n"
+    r = generated_banner("//")
+    r += "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n"
     if with_access_functions:
         r += "#include <stdint.h>\n"
         r += "#ifdef CSR_ACCESSORS_DEFINED\n"
@@ -168,7 +172,7 @@ def get_csr_header(regions, constants, with_access_functions=True, with_shadow_b
 
 
 def get_csr_csv(csr_regions=None, constants=None, memory_regions=None):
-    r = ""
+    r = generated_banner("#")
 
     if csr_regions is not None:
         for name, origin, busword, obj in csr_regions: