From: lkcl <lkcl@web>
Date: Thu, 16 Sep 2021 09:23:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68f70ca9542b76e41a44d986a39042496ebe6c11;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index d61703d56..fda504a3f 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -186,6 +186,14 @@ order.
 
 ## Scalar result reduce mode
 
+Scalar Reduction per se does not exist, instead is implemented in SVP64
+as a simple and natural relaxation of the usual restriction on the Vector
+Looping which would terminate if the destination was marked as a Scalar.
+Scalar Reduction by contrast *keeps issuing Vector Element Operations*
+even though the destination register is marked as scalar.
+Thus it is up to the programmer to be aware of this and observe some
+conventions.
+
 In this mode, which is suited to operations involving carry or overflow,
 one register must be identified by the programmer as being the "accumulator".
 Scalar reduction is thus categorised by:
@@ -255,6 +263,13 @@ parallel optimisation of the scalar reduce operation: it's just that
 as far as the user is concerned, all exceptions and interrupts **MUST**
 be precise.
 
+It is also possible, using this mode, to perform iterative computations.
+Setting the source register to be one greater or one less than the
+destination will result in a cumulative cascade of element-based
+operations being issued to the underlying hardware, where standard
+Register Hazard observance is expected and required.  "Reverse Gear"
+may prove useful in some circumstances.
+
 ## Vector result reduce mode
 
 Vector result reduce mode may utilise the destination vector for