From: Jacob Lifshay Date: Wed, 21 Sep 2022 22:41:55 +0000 (-0700) Subject: add description of prefix-code decode X-Git-Tag: opf_rfc_ls005_v1~335 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=68fdcecd75fed86414e0b116e1ea174236c573be;p=libreriscv.git add description of prefix-code decode --- diff --git a/openpower/prefix_codes.mdwn b/openpower/prefix_codes.mdwn index 3158de09a..1a6ffb21d 100644 --- a/openpower/prefix_codes.mdwn +++ b/openpower/prefix_codes.mdwn @@ -11,11 +11,39 @@ This is useful for Huffman codes, and other prefix-codes, which are used a lot i `pcdec RT,RA,RB,RC,imm` -if `imm` is 1 TODO FIXME + |0 |6 |11 |16 |21 |26 |31 | + | PO | RT | RA | RB | RC | XO | imm | + +if `imm` is 1, at most one code-word is decoded -- useful for things like DEFLATE that alternate code words with other bits, or use multiple binary code trees. if `imm` is 0, it decodes multiple code-words + +The binary code tree is encoded in `RA` like so: + +``` +t[i] = (RA >> i) & 0x1 + + | + +-----------+-----------+ + | | + 0 1 + | | + +---t[2]----+ +---t[3]----+ + | | | | + 0 1 0 1 + | | | | + +t[4]-+ +t[5]-+ +t[6]-+ +t[7]-+ + | | | | | | | | + 0 1 0 1 0 1 0 1 + | | | | | | | | +t[8] t[9] t[10] t[11] t[12] t[13] t[14] t[15] + +and so on for t[16..] +``` + +Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RB in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >6-bits, so SO/OV/OV32 are set, and decoding stops. # [DRAFT] Prefix-code decode -VA-Form +sorta-VA-Form * pcdec RT,RA,RB,RC,imm