From: lkcl <lkcl@web>
Date: Thu, 23 Jan 2020 14:11:08 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=691c05655df1f5c18d42e26b21b4bb401c18bff3;p=libreriscv.git

---

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index b972d1847..94db5b6c2 100644
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -148,6 +148,5 @@ The reasons for doing a proper modularisation job are several-fold:
 Find appropriate tutorials for nmigen and yosys, as well as symbiyosys.
 
 * Although a verilog example this is very useful to do <https://symbiyosys.readthedocs.io/en/latest/quickstart.html#first-step-a-simple-bmc-example>
-* There exist several nmigen examples which are also executable <https://github.com/m-labs/nmigen/tree/master/examples/>
 * This tutorial looks pretty good and will get you started <http://blog.lambdaconcept.com/doku.php?id=nmigen:nmigen_install> and walks not just through simulation, it takes you through using gtkwave as well.
-
+* There exist several nmigen examples which are also executable <https://github.com/m-labs/nmigen/tree/master/examples/> exactly as described in the above tutorial (python3 filename.py -h)