From: Luke Kenneth Casson Leighton Date: Fri, 17 Jun 2022 13:20:44 +0000 (+0100) Subject: whoops on an OR rather than an AND X-Git-Tag: sv_maxu_works-initial~388 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6930c4f17678943b91ca6bd80bf932b7e977c638;p=openpower-isa.git whoops on an OR rather than an AND --- diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index f1aadd73..7ac8c4b4 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -980,7 +980,7 @@ class PowerDecodeSubset(Elaboratable): comb += self.do_copy("fn_unit", Function.TRAP) comb += self.do_copy("insn_type", internal_op) # SPR pipe must *not* receive MMU or TRAP SPRs - with m.Elif(is_spr_mv & ((fn == Function.MMU) & ~is_mmu_spr) | + with m.Elif(is_spr_mv & ((fn == Function.MMU) & ~is_mmu_spr) & ((fn == Function.TRAP) & ~is_trap_spr)): comb += self.do_copy("fn_unit", Function.NONE) comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)