From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 16:32:18 +0000 (-0700)
Subject: Update README.md from master
X-Git-Tag: working-ls180~1208^2~254
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6931a3a47da5119ac44449ef117f3985e2fda417;p=yosys.git

Update README.md from master
---

diff --git a/README.md b/README.md
index e6be0f37e..19306cda3 100644
--- a/README.md
+++ b/README.md
@@ -366,7 +366,7 @@ Verilog Attributes and non-standard features
 
 - When defining a macro with `define, all text between triple double quotes
   is interpreted as macro body, even if it contains unescaped newlines. The
-  tipple double quotes are removed from the macro body. For example:
+  triple double quotes are removed from the macro body. For example:
 
       `define MY_MACRO(a, b) """
          assign a = 23;
@@ -459,7 +459,7 @@ Non-standard or SystemVerilog features for formal verification
   supported in any clocked block.
 
 - The syntax ``@($global_clock)`` can be used to create FFs that have no
-  explicit clock input ($ff cells). The same can be achieved by using
+  explicit clock input (``$ff`` cells). The same can be achieved by using
   ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
   is marked with the ``(* gclk *)`` Verilog attribute.
 
@@ -472,7 +472,7 @@ from SystemVerilog:
 
 - The ``assert`` statement from SystemVerilog is supported in its most basic
   form. In module context: ``assert property (<expression>);`` and within an
-  always block: ``assert(<expression>);``. It is transformed to a $assert cell.
+  always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
 
 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
   also supported. The same limitations as with the ``assert`` statement apply.