From: Luke Kenneth Casson Leighton Date: Sat, 10 Nov 2018 20:32:15 +0000 (+0000) Subject: macro-ify rv_sr and rv_sl X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=693597b25ae517601de3bb654119e0eec492b5b2;p=riscv-isa-sim.git macro-ify rv_sr and rv_sl --- diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 0a525ea..67c39e3 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -587,40 +587,31 @@ OP_M64_FN( mulhu , sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t ) OP_M64_FN( mulhsu, sv_sreg_t, sv_reg_t, sv_sreg_t, int64_t, uint64_t, int64_t ) OP_M64_FN( mulh , sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t ) -sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs, - unsigned int dflt_bitwidth) -{ - uint8_t bitwidth = _insn->src_bitwidth; - uint64_t vlhs = 0; - uint64_t vrhs = 0; - if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { - sv_reg_t result = lhs << rv_and(rhs, sv_reg_t(dflt_bitwidth-1U)); - fprintf(stderr, "sl result %lx %lx %lx\n", - (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(result)); - return result; - } - uint64_t result = vlhs << (vrhs & (bitwidth-1)); - return rv_int_op_finish(lhs, rhs, result, bitwidth); +#define OP_SHF_FN( fname, SLHSTYPE, SRHSTYPE, SRESTYPE, \ + LHSTYPE, RHSTYPE, RESTYPE ) \ +SRESTYPE sv_proc_t::rv##fname (SLHSTYPE const & lhs, SRHSTYPE const & rhs, \ + unsigned int dflt_bitwidth) \ +{ \ + uint8_t bitwidth = _insn->src_bitwidth; \ + LHSTYPE vlhs = 0; \ + RHSTYPE vrhs = 0; \ + if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { \ + RESTYPE result = lhs fname rv_and(rhs, sv_reg_t(dflt_bitwidth-1U)); \ + fprintf(stderr, "%s result %lx %lx %lx\n", \ + xstr(fname), (LHSTYPE)lhs, (RHSTYPE)rhs, (RESTYPE)result); \ + return SRESTYPE(result); \ + } \ + RESTYPE result = vlhs fname (vrhs & (bitwidth-1)); \ + fprintf(stderr, "%s result %lx %lx %lx bw %d\n", \ + xstr(fname), (LHSTYPE)lhs, (RHSTYPE)rhs, (RESTYPE)result, bitwidth); \ + return rv_int_op_finish(lhs, rhs, result, bitwidth); \ } -sv_reg_t sv_proc_t::rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs, - unsigned int dflt_bitwidth) -{ - uint8_t bitwidth = _insn->src_bitwidth; - uint64_t vlhs = 0; - uint64_t vrhs = 0; - if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { - sv_reg_t result = lhs >> rv_and(rhs, sv_reg_t(dflt_bitwidth-1U)); - fprintf(stderr, "sr result %lx %lx %lx\n", - (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(result)); - return result; - } - uint64_t result = vlhs >> (vrhs & (bitwidth-1)); - sv_reg_t sresult = rv_int_op_finish(lhs, rhs, result, bitwidth); - fprintf(stderr, "sr result %lx %lx %lx bw %d\n", - (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(sresult), bitwidth); - return sresult; -} +#define _sl << +#define _sr >> + +OP_SHF_FN ( _sl, sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t ) +OP_SHF_FN ( _sr, sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t ) #define lt < #define gt >