From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Apr 2020 08:33:22 +0000 (+0200)
Subject: build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
X-Git-Tag: 24jan2021_ls180~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69462e66690b606183caa410783402df721d8d86;p=litex.git

build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
---

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 7507264b..53b16507 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -275,11 +275,28 @@ class XilinxDDRInputS7:
     def lower(dr):
         return XilinxDDRInputImplS7(dr.i, dr.o1, dr.o2, dr.clk)
 
+# 7-Series SDROutput -------------------------------------------------------------------------------
+
+class XilinxSDROutputS7:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDROutputImplS7(dr.i, dr.i, dr.o, dr.clk)
+
+
+# 7-Series SDRInput --------------------------------------------------------------------------------
+
+class XilinxSDRInputS7:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDRInputImplS7(dr.i, dr.o, Signal(), dr.clk)
+
 # 7-Series Special Overrides -----------------------------------------------------------------------
 
 xilinx_s7_special_overrides = {
     DDROutput: XilinxDDROutputS7,
-    DDRInput:  XilinxDDRInputS7
+    DDRInput:  XilinxDDRInputS7,
+    SDROutput: XilinxSDROutputS7,
+    SDRInput:  XilinxSDRInputS7,
 }
 
 # Ultrascale DDROutput -----------------------------------------------------------------------------
@@ -322,11 +339,28 @@ class XilinxDDRInputUS:
     def lower(dr):
         return XilinxDDRInputImplUS(dr.i, dr.o1, dr.o2, dr.clk)
 
+# Ultrascale SDROutput -----------------------------------------------------------------------------
+
+class XilinxSDROutputUS:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDROutputImplUS(dr.i, dr.i, dr.o, dr.clk)
+
+
+# Ultrascale SDRInput ------------------------------------------------------------------------------
+
+class XilinxSDRInputUS:
+    @staticmethod
+    def lower(dr):
+        return XilinxDDRInputImplUS(dr.i, dr.o, Signal(), dr.clk)
+
 # Ultrascale Specials Overrides --------------------------------------------------------------------
 
 xilinx_us_special_overrides = {
     DDROutput: XilinxDDROutputUS,
-    DDRInput:  XilinxDDRInputUS
+    DDRInput:  XilinxDDRInputUS,
+    SDROutput: XilinxSDROutputUS,
+    SDRInput:  XilinxSDRInputUS,
 }
 
 # Yosys Run ----------------------------------------------------------------------------------------