From: lkcl <lkcl@web>
Date: Wed, 20 Apr 2022 19:30:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2666
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6948e4543e0095ccf696fd5c83777d1783cc1db2;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 3799f22d8..a26477dc7 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -202,6 +202,8 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical
 to RC extended to SVP64 numbering, including whether RC is set Scalar or
 Vector.
 
+## msubed
+
 The pseudocode for `msubed RT, RA, RB, RC`` is:
 
     prod[0:127] = (RA) * (RB)
@@ -213,6 +215,8 @@ Note that RC is not sign-extended to 64-bit.  In a Vector Loop
 it contains the top half of the previous multiply-with-subtract,
 and the current product must be subtracted from it.
 
+## madded
+
 The pseudocode for `madded RT, RA, RB, RC` is:
 
     prod[0:127] = (RA) * (RB)