From: lkcl <lkcl@web>
Date: Sat, 5 Mar 2022 23:10:04 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=69612f4c0d3f64bbccd4783eb1a33f51d18bf11f;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index f6c2265b1..2948c2adb 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -514,6 +514,10 @@ uint64_t gorc64(uint64_t RA, uint64_t RB)
 
 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 
+
+https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf
+
+
 ## SPRs to set modulo and degree
 
 to save registers and make operations orthogonal with standard