From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 2 Apr 2015 09:17:33 +0000 (+0800)
Subject: move gpio from cpu.peripherals to com
X-Git-Tag: 24jan2021_ls180~2404
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=696819cc7f9fdd405dfafc108f55960bf2055e5e;p=litex.git

move gpio from cpu.peripherals to com
---

diff --git a/misoclib/com/gpio/__init__.py b/misoclib/com/gpio/__init__.py
new file mode 100644
index 00000000..e8ae09db
--- /dev/null
+++ b/misoclib/com/gpio/__init__.py
@@ -0,0 +1,27 @@
+from migen.fhdl.std import *
+from migen.genlib.cdc import MultiReg
+from migen.bank.description import *
+
+class GPIOIn(Module, AutoCSR):
+	def __init__(self, signal):
+		self._in = CSRStatus(flen(signal))
+		self.specials += MultiReg(signal, self._in.status)
+
+class GPIOOut(Module, AutoCSR):
+	def __init__(self, signal):
+		self._out = CSRStorage(flen(signal))
+		self.comb += signal.eq(self._out.storage)
+
+class GPIOInOut(Module):
+	def __init__(self, in_signal, out_signal):
+		self.submodules.gpio_in = GPIOIn(in_signal)
+		self.submodules.gpio_out = GPIOOut(out_signal)
+
+	def get_csrs(self):
+		return self.gpio_in.get_csrs() + self.gpio_out.get_csrs()
+
+class Blinker(Module):
+	def __init__(self, signal, divbits=26):
+		counter = Signal(divbits)
+		self.comb += signal.eq(counter[divbits-1])
+		self.sync += counter.eq(counter + 1)
diff --git a/misoclib/cpu/peripherals/gpio/__init__.py b/misoclib/cpu/peripherals/gpio/__init__.py
deleted file mode 100644
index e8ae09db..00000000
--- a/misoclib/cpu/peripherals/gpio/__init__.py
+++ /dev/null
@@ -1,27 +0,0 @@
-from migen.fhdl.std import *
-from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
-
-class GPIOIn(Module, AutoCSR):
-	def __init__(self, signal):
-		self._in = CSRStatus(flen(signal))
-		self.specials += MultiReg(signal, self._in.status)
-
-class GPIOOut(Module, AutoCSR):
-	def __init__(self, signal):
-		self._out = CSRStorage(flen(signal))
-		self.comb += signal.eq(self._out.storage)
-
-class GPIOInOut(Module):
-	def __init__(self, in_signal, out_signal):
-		self.submodules.gpio_in = GPIOIn(in_signal)
-		self.submodules.gpio_out = GPIOOut(out_signal)
-
-	def get_csrs(self):
-		return self.gpio_in.get_csrs() + self.gpio_out.get_csrs()
-
-class Blinker(Module):
-	def __init__(self, signal, divbits=26):
-		counter = Signal(divbits)
-		self.comb += signal.eq(counter[divbits-1])
-		self.sync += counter.eq(counter + 1)
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index c24c0456..c918686e 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -6,16 +6,14 @@ from migen.fhdl.std import *
 from mibuild.generic_platform import ConstraintError
 
 from misoclib.others import mxcrg
-from misoclib.mem import sdram
 from misoclib.mem.sdram.module import MT46V32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
 from misoclib.mem.flash import norflash16
-from misoclib.cpu.peripherals import gpio
 from misoclib.video import framebuffer
 from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
-
+from misoclib.com import gpio
 from misoclib.com.liteeth.phy import LiteEthPHY
 from misoclib.com.liteeth.mac import LiteEthMAC