From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Nov 2021 16:22:18 +0000 (+0000)
Subject: read latch on regfile ports was fine, the combinatorial loop
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6969a866299ddfbcaef00e1434d14d0d1fb4540a;p=soc.git

read latch on regfile ports was fine, the combinatorial loop
is in the hazard detection on instruction issue
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 6164aea6..82525d25 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -470,10 +470,10 @@ class NonProductionCore(ControlBase):
                     rdl = fu.rd_latches[rname]
                 # latch to make the read immediately available on issue cycle
                 # after the read cycle, use the latched copy
-                #with m.If(fu.issue_i):
-                comb += read.eq(_read)
-                #with m.Else():
-                #    comb += read.eq(rdl)
+                with m.If(fu.issue_i):
+                    comb += read.eq(_read)
+                with m.Else():
+                    comb += read.eq(rdl)
 
                 # connect request-read to picker input, and output to go-rd
                 addr_en = Signal.like(read, name="addr_en_"+name)
@@ -516,7 +516,8 @@ class NonProductionCore(ControlBase):
                 # read the write-hazard bitvector (wv) for any bit that is
                 wvchk_en = Signal(len(wvchk.ren), name="wv_chk_addr_en_"+name)
                 issue_active = Signal(name="rd_iactive_"+name)
-                comb += issue_active.eq(self.instruction_active & rdflags[i])
+                # XXX combinatorial loop here
+                #comb += issue_active.eq(self.instruction_active & rdflags[i])
                 with m.If(issue_active):
                     if rfile.unary:
                         comb += wvchk_en.eq(read)