From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 17:24:33 +0000 (+0100)
Subject: correct XER variable names
X-Git-Tag: div_pipeline~1020
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6970df03f7b79c8e577f16d46f07f3ed25b99657;p=soc.git

correct XER variable names
---

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index d390c501..afcf12e7 100644
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -40,15 +40,17 @@ class Driver(Elaboratable):
         a = dut.i.rs
         b = dut.i.rb
         ra = dut.i.ra
-        carry_in = dut.i.carry_in
-        so_in = dut.i.so
-        carry_out = dut.o.carry_out
+        carry_in = dut.i.xer_ca[0]
+        carry_in32 = dut.i.xer_ca[1]
+        so_in = dut.i.xer_so
+        carry_out = dut.o.xer_ca
         o = dut.o.o
 
         # setup random inputs
         comb += [a.eq(AnyConst(64)),
                  b.eq(AnyConst(64)),
                  carry_in.eq(AnyConst(1)),
+                 carry_in32.eq(AnyConst(1)),
                  so_in.eq(AnyConst(1))]
 
         comb += dut.i.ctx.op.eq(rec)