From: N. Engelhardt <nak@symbioticeda.com>
Date: Thu, 12 Mar 2020 10:18:35 +0000 (+0100)
Subject: Merge pull request #1751 from boqwxp/add_assert
X-Git-Tag: working-ls180~760
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6986371bacb9ace908cc2156c2eed41cb1303765;p=yosys.git

Merge pull request #1751 from boqwxp/add_assert

Extend `add` command to allow adding $assert cells.
---

6986371bacb9ace908cc2156c2eed41cb1303765
diff --cc passes/cmds/add.cc
index 62c253bed,459b29f35..7b76f3d4a
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@@ -22,9 -22,45 +22,45 @@@
  USING_YOSYS_NAMESPACE
  PRIVATE_NAMESPACE_BEGIN
  
+ static bool is_formal_celltype(const std::string &celltype)
+ {
+ 	if(celltype == "assert" || celltype == "assume" || celltype == "live" || celltype == "fair" || celltype == "cover")
+ 		return true;
+ 	else
+ 		return false;
+ }
+ 
+ static void add_formal(RTLIL::Module *module, const std::string &celltype, const std::string &name, const std::string &enable_name)
+ {
+ 	std::string escaped_name = RTLIL::escape_id(name);
+ 	std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : "";
+ 	RTLIL::Wire *wire = module->wire(escaped_name);
+ 	log_assert(is_formal_celltype(celltype));
+ 
+ 	if (wire == nullptr) {
+ 		log_error("Could not find wire with name \"%s\".\n", name.c_str());
+ 	}
+ 	else {
+ 		RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
+ 		formal_cell->setPort(ID(A), wire);
+ 		if(enable_name == "") {
+ 			formal_cell->setPort(ID(EN), State::S1);
+ 			log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
+ 		}
+ 		else {
+ 			RTLIL::Wire *enable_wire = module->wire(escaped_enable_name);
+ 			if(enable_wire == nullptr)
+ 				log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
+ 
+ 			formal_cell->setPort(ID(EN), enable_wire);
+ 			log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
+ 		}
+ 	}
+ }
+ 
  static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
  {
 -	RTLIL::Wire *wire = NULL;
 +	RTLIL::Wire *wire = nullptr;
  	name = RTLIL::escape_id(name);
  
  	if (module->count_id(name) != 0)